Page 24 of 32
IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
Figure 6: External Program Memory Read Cycle
TLHLL
ALE
TLLPL
TLLIV
TPLIV
TAVLL
TPLPH
PSENn/EPSENn
TPLAZ
TPXIZ
TPXIX
TLLAX
A0-A7
PORT0/PORT5
PORT2/PORT6
INSTR IN
A0-A7
TAVIV
A8-A15
A8-A15
Figure 7: External Data Memory Read Cycle
ALE
TLLDV
TWHLH
PSENn
RDn
TLLWL
TRLRH
TLLAX
TAVLL
TRLAZ
TRLDV
TRHDZ
TRHDX
A0-A7 FROM R OR DPL
A0-A7 FROM PCL
INSTR. IN
PORT0
PORT2
DATA IN
TAVWL
TAVDV
P2.0-P2.7 OR A8-A15 FROM DPH
A8-A15 FROM PCH
Copyright ã 2000
innovASIC
[_________The End of Obsolescenceä