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IA59032 参数 Datasheet PDF下载

IA59032图片预览
型号: IA59032
PDF下载: 下载PDF文件 查看货源
内容描述: 32位高速微处理器片 [32-Bit High Speed Microprocessor Slice]
分类和应用: 微处理器
文件页数/大小: 17 页 / 74 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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Page 7 of 17  
IA59032  
Data Sheet  
32-Bit High Speed Microprocessor Slice  
I/O SIGNAL DESCRIPTION  
The diagram below describes the I/O characteristics for each signal on the IC. The signal names correspond  
to the signal names on the pinout diagrams provide.  
I/O CHARACTERISTICS:  
DESCRIPTION  
SIGNAL NAME  
I/O  
The five address inputs to the on board RAM used to select word to be displayed  
throught the A-port  
A(4:0)  
I
Addresses which select the word of on board RAM which is to be diplayed through the B-  
port and into which data is written when the clock is low.  
B(4:0)  
I(8:0)  
I
I
The nine instruction control lines. Used to determine what data sources will be applied  
to the ALU(I(2:0)), what function the ALU will perform (I(5:3)), and what data is to be  
deposited in the Q-register or on board RAM (I(8:6)).  
Signal paths at the MSB of the on-board RAM and the Q-register which are used for  
shifting data. When the destination code on I(8:6) indicates an up shift(Octal 6 or 7) the  
three state outputs are enabled and the MSB of the Q-register is available on the Q31 pin.  
Otherwise the pins appear as inputs. When the destination code calls for a down shift the  
pins are used as the data inputs to the MSB of the Q-register (Octal 4) and RAM (Octal 4  
and 5).  
Q31  
RAM31  
I/O  
Shift lines similar to the Q31 and RAM 31; however the decription is applied to the LSB  
of RAM and the Q-register.  
Q0  
RAM0  
I/O  
I
Direct data inputs which may be selected as one of the ALU data sources for entering  
data into the device. D0 is the LSB.  
Tri-statable outputs which, when enabled, display either the data on the A-port of the  
register stack or the outputs of the ALU as determined by the destination code I(8:6).  
D(31:0)  
Y(31:0)  
O
Output enable. When HIGH, the Y outputs are in the high impedance state. When  
LOW, either the contents of the A-register or the outputs of the ALU are displayed on  
Y(31:0).  
OEn  
I
Overflow. This signal indicates that an overflow into the sign bit has occurred as a result  
of a two's complement operation.  
OVR  
O
This output, when HIGH, indicates that the result of an ALU operation is zero.  
The most significnt ALU output bit.  
FZERO  
F31  
O
O
The carry-in to the ALU.  
Cn  
I
The carry-out of the ALU.  
Cn32  
O
The clock input. The clock low time is the write enable to the on-board dual port RAM,  
including set-up time fot the A and B - portregisters. The A and B- port outputs change  
while the clock is HIGH. The Q-register is latched on the clock LOW-to-HIGH  
transition.  
CP  
I
Copyright ã 2000  
innovASIC  
[_________The End of Obsolescenceä