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IA59032 参数 Datasheet PDF下载

IA59032图片预览
型号: IA59032
PDF下载: 下载PDF文件 查看货源
内容描述: 32位高速微处理器片 [32-Bit High Speed Microprocessor Slice]
分类和应用: 微处理器
文件页数/大小: 17 页 / 74 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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Page 6 of 17  
IA59032  
Data Sheet  
32-Bit High Speed Microprocessor Slice  
The 32-bit data output field (Y) features three-state outputs. An output control (OEn) is used to enable the  
three-state outputs. When OEn is HIGH, the Y outputs are in the high-impedance state.  
A two input mux is also used at the data output such that either the A-port of the RAM or the ALU outputs  
(F) are selected at the device Y outputs. I(8:6) inputs control this selection.  
As was discussed previously, the RAM inputs are driven from a three-input mux. This allows the ALU  
outputs to be entered non-shifted, shifted up one position (X2) or shifted down one position (/2). The  
shifter has two ports; one is labeled RAM0 and the other is RAM31. Both of these ports consist of a buffer  
driver with a three-state output and an input to the mux. Thus, in the shift up mode, the RAM31 buffer is  
enabled and the RAM0 mux input is enabled. Likewise, is in the shift down mode, the RAM0 buffer and  
RAM31 input are enabled. In the no-shift mode, both buffers are in the high-impedance state and the mux  
inputs are not selected. The I(8:6) inputs control the shifter.  
Similarly, the Q register is driven from a 3-input mux. In the no-shift mode, the mux enters the ALU data  
into the Q register. In either the shift-up or shift-down mode, the mux selects the Q register data  
appropriately shifted up or down. The Q shifter also has two ports; Q0 and Q31. The operations of these  
two ports are similar to the RAM shifter and are also controlled from the I(8:6) inputs.  
The clock input controls the RAM, Q register, and the A and B data latches. When enabled, data is clocked  
into the Q register on the LOW to HIGH transition of the clock. When CP is HIGH, the A and B latches  
are open and will pass whatever data is present at the RAM outputs. When CP is LOW, the latches are  
closed and will retain the last data entered. New data will be written into the RAM defined by the B address  
field when the clock input is LOW.  
Copyright ã 2000  
innovASIC  
[_________The End of Obsolescenceä  
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