IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Table 97. Instruction Set Summary (Continued)
Instruction
Opcode - Hex
Flags Affected
Bytes
3–6
–
Mnemonic
XCHG
Description
Exchange word reg with AX
Exchange AX with word reg
Byte 1
90
+rw
Byte 2
–
–
O
–
D
–
I
–
T
–
S
–
Z
–
A
–
P
–
C
–
–
Exchange byte reg with r/byte
Exchange r/m8 with byte reg
Exchange word reg with r/m16
Exchange r/m16 with word reg
86
87
/r
/r
/r
/r
–
–
–
–
–
–
XLAT
XLATB
XOR
Set AL to memory byte segment
:[BX+unsigned AL]
Set AL to memory byte DS
:[BX+unsigned AL]
D7
D7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
XOR imm8 with AL
34
35
80
ib
iw
/6
–
–
0
R
R
U
R
0
XOR imm16 with AX
XOR imm8 with r/m8
ib
XOR imm16 with r/m16
XOR sign-extended imm8 with
r/m16
81
83
/6
/6
iw
ib
XOR byte reg with r/m8
XOR word reg with r/m16
XOR r/m8 with byte reg
XOR r/m16 with word reg
30
31
32
33
/r
/r
/r
/r
–
–
–
–
7.1
Key to Abbreviations Used in Instruction Set Summary Table
Abbreviations used in the Instruction Set Summary Table are explained below.
7.1.1 Operand Address Byte
The operand address byte is configured as shown below.
7
6
5
4
3
2
1
0
mod field aux field r/m field
7.1.2 Modifier Field
The modifier field is defined below.
mod Description
11
00
01
10
r/m is treated as a register field
DISP = 0, disp-low and disp-high are absent, address displacement is 0
DISP = disp-low sign-extended to 16-bits, disp-high is absent
DISP = disp-high:disp-low
IA211110517-02
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