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FIDO2100 参数 Datasheet PDF下载

FIDO2100图片预览
型号: FIDO2100
PDF下载: 下载PDF文件 查看货源
内容描述: fido2100 3端口工业以太网交换机DLR与IEEE 1588 [fido2100 3-Port Industrial Ethernet DLR Switch with IEEE 1588]
分类和应用: 以太网工业以太网
文件页数/大小: 84 页 / 2688 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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fido2100 3-Port Industrial Ethernet DLR Switch with IEEE1588  
Data Sheet  
April 10, 2013  
Pin Signal Name  
36 p2_txd[0]  
37 p2_txd[1]  
38 p2_txd[2]  
39 vcck  
Type  
LQFP Pin Descriptions  
output port 2 mii, transmit data bit 0 to PHY  
output port 2 mii, transmit data bit 1 to PHY  
output port 2 mii, transmit data bit 2 to PHY  
power 1.8 V digital core supply voltage  
ground digital core ground  
40 gndk  
41 gndio  
ground i/o ground  
42 vcc3io  
power 3.3 V i/o supply voltage  
43 p2_txd[3]  
44 p2_rxc  
45 p2_rxdv  
46 p2_rxer  
47 gndo  
output port 2 mii, transmit data bit 3 to PHY  
input  
input  
input  
port 2 mii, receive clock from PHY  
port 2 mii, receive data valid from PHY  
port 2 mii, receive data error from PHY  
ground i/o ground  
48 vdd3o  
power 3.3 V i/o supply voltage  
49 p2_rxd[0]  
50 p2_rxd[1]  
51 p2_rxd[2]  
52 p2_rxd[3]  
53 p2_col  
54 p2_crs  
55 vcc3io  
input  
input  
input  
input  
input  
input  
port 2 mii, receive data bit 0 from PHY  
port 2 mii, receive data bit 1 from PHY  
port 2 mii, receive data bit 2 from PHY  
port 2 mii, receive data, bit 3 from PHY  
port 2 mii, collision from PHY  
port 2 mii, carrier sense from PHY  
power 3.3 V i/o supply voltage  
ground i/o ground  
56 gndio  
57 gndk  
58 vcck  
ground digital core ground  
power 1.8 V digital core supply voltage  
59 p2_lnk_stts  
60 p2_led_grn  
61 p2_led_ylw  
62 reset_n  
63 sys_clk  
64 test  
65 cpu_txen  
66 vcc18a_pll  
67 gnda_pll  
68 cpu_txer  
69 cpu_txc  
70 cpu_txd[0]  
71 vcck  
input  
port 2 mii, link status from PHY (1:link pass, 0:link fail)  
output port 2 mii,, green led  
output port 2 mii,, yellow led  
input  
input  
input  
input  
power 1.8 V analog supply voltage  
ground analog ground  
input  
output cpu mii, 25 MHz transmit clock to CPU  
input cpu mii, transmit data bit 0 from CPU  
chip reset, active low (internal pull-up)  
25 MHz system clock  
test, active high (internal pull-down)  
cpu mii, transmit enable from CPU  
cpu mii, transmit error from CPU  
power 1.8 V digital core supply voltage  
ground digital core ground  
ground i/o ground  
72 gndk  
73 gndio  
74 vcc3io  
power 3.3 V i/o supply voltage  
75 cpu_txd[1]  
input  
cpu mii, transmit data bit 1 from CPU  
27  
support@innovasic.com  
Document #: IA211111101-04  
UNCONTROLLED WHEN PRINTED OR COPIED  
1-505-883-5263  
1-888-824-4184  
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