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AM188ES-33VIW 参数 Datasheet PDF下载

AM188ES-33VIW图片预览
型号: AM188ES-33VIW
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器 [8-Bit/16-Bit Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 154 页 / 1714 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA186ES/IA188ES  
Data Sheet  
8-Bit/16-Bit Microcontrollers  
November 15, 2011  
DMA Control Bits  
DMA Bits  
000b  
001b  
010b  
011b  
100b  
101b  
110b  
111b  
Receive  
No DMA  
DMA0  
DMA1  
Reserved Reserved  
DMA0  
DMA1  
No DMA  
No DMA  
Transmit  
No DMA  
DMA1  
DMA0  
No DMA  
No DMA  
DMA0  
DMA1  
DMA transfers to both serial ports are destination-synchronized operations. When the  
transmit holding register is empty, a new transfer is requested, corresponding with the  
assertion of the THRE bit in the status register in non-DMA mode. However, when  
configured for DMA transfers, the respective transmit interrupt is disabled without  
regard for the TXIE bit.  
DMA transfers from both serial ports are source-synchronized operations. When the  
receive holding register contains valid data, a new transfer is requested,  
corresponding with the assertion of the RDR bit in the status register in non-DMA  
mode. However, when configured for DMA receives, the respective receive interrupt  
is disabled without regard for the RXIE bit. This is despite the fact that the RSIE bit  
may still permit receive status interrupts, depending on its setting.  
DMA transfers do not preclude the use of hardware handshaking.  
If either or both serial ports are configured for DMA transfers, the DMA request is  
internally generated and the corresponding external DMA signals, drq0 and/or drq1  
do not play a role.  
Bit [12]RSIE Receive Status Interrupt Enable When an exception occurs during  
data reception, an interrupt request is generated if enabled by this bit (RSIE = 1).  
Interrupt requests are made for the error conditions listed (BRK0, BRK1, OER, PER, and  
FER) in the serial port status register.  
Bit [11]BRK Send Break When this bit is set to 1, the txd pin is driven low  
overriding any data that may be in the course of being shifted out of the transmit shift  
register.  
Note: See the definitions of long and short break in the Serial Port Status  
register definition.  
®
IA211050902-19  
UNCONTROLLED WHEN PRINTED OR COPIED  
http://www.innovasic.com  
Customer Support:  
Page 85 of 154  
1-888-824-4184  
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