IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Bit [6]—THRE Transmit Holding Register Empty → When this bit is 1, it indicates that
the corresponding transmit holding register is ready to accept data. This is a read-only
bit.
Bit [5]—FER Framing Error Detected → When the receiver samples the rxd line as low
when a stop bit is expected (line high), a framing error is generated setting this bit.
Note: This bit should be reset by software.
Bit [4]—OER Overrun Error Detected → When new data overwrites valid data in the
receive register (because it has not been read), an overrun error is detected setting this bit.
Note: This bit should be reset by software.
Bit [3]—PER Parity Error Detected → When a parity error is detected in either mode 1
or 3, this bit is set.
Note: This bit should be reset by software.
Bit [2]—TEMT Transmitter Empty → When both the transmit shift register and the
transmit register are empty, this bit is set indicating to software that it is safe to disable
the transmitter. This bit is read-only.
Bit [1]—HS0 Handshake Signal 0 → This bit is the inverted value of cts_n and is read
only.
Bit [0]—RES Reserved.
5.1.26 SP0CT (080h) and SP1CT (010h)
Serial Port ConTrol Registers. These registers control both transmit and receive parts of the
respective serial ports. The value of the SP0CT and SP1CT registers is 0000h at reset (see
Table 42).
Table 42. Serial Port Control Registers
15 14 13
DMA
12
11
10
9
8
7
6
5
4
3
2
1
0
RSIE BRK TB8 FC TXIE RXIE TMODE RMODE EVN PE
MODE
Bits [15–13]—DMA DMA Control Field → These bits set up the respective ports for use
with DMA transfers as shown below.
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