IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
Table 88. Interrupt Acknowledge Cycle Timing
a
a
No.
Name
Description
Min
Max
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
10
0
–
–
General Timing Responses
3
tCHSV
tCLSH
tCLDV
tCHDX
tCHLH
tLHLL
tCHLL
tAVLL
tCLAZ
tDXDL
Status Active Delay
Status Inactive Delay
Data Valid Delay
0
0
0
0
0
6
6
4
7
12
–
8
Status Hold Time
9
ale Active Delay
8
10
11
12
15
19
20
21
22
23
31
68
ale Width
tCLCH-5
–
ale Inactive Delay
0
8
ad Address Valid to ale Low
ad Address Float Delay
den_n Inactive to dt/r_n Low
tCLCH
–
0
0
12
–
tCVCTV Control Active Delay 1
tCVDEX den_n Inactive Delay
tCHCTV Control Active Delay 2
0
10
9
0
0
10
–
tLHAV
tCVCTX Control Inactive Delay
tCHAV
clkouta High to a Address Valid
ale High to Address Valid
7.5
0
10
8
0
a
In nanoseconds.
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