IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
0ns
20ns
9
40ns
60ns
80ns
100ns
120ns
28
140ns
160ns
180ns
KLC0
clkouta
19a-0
Address
a19–a0
11
ale
ela
27
10
26
rd_n
_drn
80
25
27
81
lcs_n
79
82
85
rfhs_
rfsh_n
86
Figure 17. PSRAM Refresh Cycle
Table 87. PSRAM Refresh Cycle
a
a
No.
Name
Comment
Min
Max
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
10
0
–
–
General Timing Responses
9
tCHLH
tLHLL
tCHLL
ale Active Delay
ale Width
0
8
–
8
10
11
tCLCH-5
0
ale Inactive Delay
Read/Write Cycle Timing Responses
25
26
27
28
80
81
tCLRL
tRLRH
tCLRH
tRHLH
rd_n Active Delay
0
10
–
rd_n Pulse Width
tCLCL
rd_n Inactive Delay
rd_n Inactive to ale High
0
10
–
tCLCH
tCLCLX lcs_n Inactive Delay
tCLCSL lcs_n Active Delay
0
0
9
9
Refresh Cycle Timing Responses
79
82
85
86
tCHRFD clkouta High to rfsh_n Valid
0
0
12
12
–
tCLRF
tRFCY
tLCRF
clkouta High to rfsh_n Invalid
rfsh_n Cycle Time
6tCLCL
lcs_n Inactive to rfsh_n Active Delay 2tCLCL NULL
a
In nanoseconds.
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IA211050831-19
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