IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Adder
Control Logic
Timer Request
20-bit Adder/Subtractor
20
drq1
drq0
Request
Selection
Logic
Transfer Counter Ch. 1
Destination Address Ch. 1
Source Address Ch. 1
Transfer Counter Ch. 0
Destination Address Ch. 0
Source Address Ch. 0
DMA
Control
Logic
Interrupt Request
Channel Control Register 1
Channel Control Register 0
20
16
Internal Address/Data Bus
Figure 10. DMA Unit
4.22 DMA Channel Control Registers
See Section 5.1.10, D1CON (0dah) and D0CON (0cah). The DMA channel control registers
specify the following:
Whether the data destination is in memory or I/O space (Bit [15])
Whether the destination address is incremented, decremented, or unchanged after each
transfer (Bits [14–13])
Whether the data source is in memory or I/O space (Bit [12])
Whether the source address is incremented, decremented, or unchanged after each
transfer (Bits [11–10])
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