IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
occurred with the NMIFLAG set. This permits system initialization code to distinguish between
a WDT reset and hardware reset and take appropriate action. The RSTFLAG is cleared by a read
or write to the WDTCON register. During a WDT reset, the external pins are not re-sampled,
ensuring that clocking, reset configuration register, and any other features that are user
programmable during reset do not change when a WDT system reset occurs. All other activities
are the same as those of a normal system reset.
4.20 Direct Memory Access
DMA frees the CPU from involvement in transferring data between memory and peripherals
over either one or both high-speed DMA channels. Data may be transferred from memory to
I/O, I/O to memory, memory to memory, or I/O to I/O. DMA channels may be connected to
asynchronous serial ports.
The IA186ES microcontroller supports the transfer of both bytes and words to and from even or
odd addresses. It does not support word transfers to memory that is configured for byte accesses.
The IA188ES does not support word transfers at all. Each data transfer will take two bus cycles
(a minimum of 8 clock cycles).
There are four sources of DMA requests for both DMA channels:
The channel request pin (drq1–drq0)
Timer2
A serial port
The system software.
Each channel may be programmed to have a different priority either to resolve a simultaneous
DMA request or to interrupt a transfer on the other channel.
4.21 DMA Operation
The PCB contains six registers for each DMA channel to control and specify the operation of the
channel (see Figure 10):
Two registers to store a 20-bit source address
Two registers to store a 20-bit destination address
One 16-bit transfer-count register
One 16-bit control register
The number of DMA transfers required is designated in the DMA Transfer Count register and
may contain up to 64 Kbytes or words. It will end automatically. DMA channel function is
defined by the Control registers. Like the other five registers, these may be changed at any time
(including during a DMA transfer) and are implemented immediately.
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