IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
4.2
Clock and Power Management
A phase-lock-loop (PLL) and a second programmable system clock output (clkoutb) are included
in the clock and power management unit. The internal clock is the same frequency as the crystal
but with a duty cycle of 45% to 55%, as a worst case, generated by the PLL obviating the need
for a 2X external clock. A POR resets the PLL (see Figure 8).
C1
Recommended
x1
range of values for
C1 and C2 are:
IA186ES/
IA188ES
C1 = 15 pF ±20%
C2 = 22 pF ±20%
x2
C2
Crystal
Figure 8. Crystal Configuration
4.3
System Clocks
If required, the internal oscillator may be driven by an external clock source that should be
connected to x1, leaving x2 unconnected.
The clock outputs, clkouta and clkoutb, may be enabled or disabled individually (SYSCON
register Bits [11–8]). These clock control bits allow one clock output to run at PLL frequency
and the other to run at the power-save frequency (see Figure 9).
Processor Internal Clock
Power-Save
x1, x2
PLL
Divisor
(/2 to /128)
Mux
clkouta
clkoutb
Drive enable
Time Delay
6 ±2.5nS
Mux
Drive enable
Figure 9. Organization of Clock
®
IA211050902-19
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