IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
4.4
Power-Save Mode
The operation of the CPU and peripheral operate at a slower clock frequency when in power save
mode, reducing power consumption and thermal dissipation. Should an interrupt occur, the
microcontroller returns to its normal operating frequency automatically on the internal clock’s
next rising edge in t3. Any clock-dependent devices should be reprogrammed for the change in
frequency during the power-save mode period.
4.5
Initialization and Reset
The res_n (Reset), the highest priority interrupt, must be held low for 1 mS during power-up to
initialize the microcontroller correctly. This operation makes the device cease all instruction
execution and local bus activity. The microcontoller begins instruction execution at physical
address FFFF0h when res_n becomes inactive and after an internal processing interval with
ucs_n is asserted and three wait states. Reset also sets up certain registers to predetermined
values and resets the WDT.
4.6
Reset Configuration Register
The data on the address/data bus (ad15–ad0 for the IA186ES and ao15–ao8 and ad7–ad0 for the
IA188ES) are written into the Reset Configuration Register when reset is low. This data is
system-dependent and is held in the Reset Configuration Register after reset is de-asserted. This
configuration data may be placed on the address/data bus by using weak external pull-up and
pull-down resistors or applied to the bus by an external driver, as the processor does not drive the
bus during reset. It is a method of supplying the software with some initial data after a reset
(e.g., option jumper positions).
4.7
Chip Selects
Chip-select generation is programmable for memories and peripherals. Programming is also
available to produce ready and wait-state generation plus latched address bits a1 and a2. For all
memory and I/O cycles, the chip-select lines are active within their programmed areas,
regardless of whether they are generated by the internal DMA unit or the CPU.
There are six chip-select outputs for memory and a further six for peripherals whether in memory
or I/O space. The memory chip-selects are able to address three memory ranges, whereas the
peripheral chip-selects are used to address 256-byte blocks that are offset from a programmable
base address. Writing to a chip-select register enables the related logic even in the event that the
pin in question has another function (e.g., where a pin is programmed to be a PIO).
4.8
Chip-Select Timing
For normal timing, the ucs_n and lcs_n outputs are asserted with the non-multiplexed address
bus.
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