IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
The value stored in a timer’s associated maximum count register determines its maximum count
value. Upon reaching it, the timer count register is reset to 0 in the same clock cycle that this
count was attained. The timer count register does not store this maximum value. Both timer0
and timer1 have a primary and a secondary maximum count register that permits each to
alternate between two discrete maximum values.
Timer0 and timer1 may have the maximum count registers configured in either primary only or
both primary and secondary. If the primary only is configured to operate, on reaching the
maximum count, the output pin will go low for one clock period. If both the primary and
secondary registers are enabled, the output pin reflects the state of the register in control at the
time. This generates the required waveform that is dependent on the two values in the maximum
count registers.
Because they are polled every fourth clock period, the timers can operate at a quarter of the
internal clock frequency. Although an external clock may be used, the timer output may take six
clock cycles to respond to the input.
4.19 Watchdog Timer
The WDT operates in real WDT fashion and may be used to prevent loss of control in the event
that software does not respond in an expected manner. The WDT is active after reset, has a
maximum timeout count, and is programmed for system reset mode. The WDT control register
(WDTCON) may be written to only once after reset. This is accomplished by writing 3333h,
then CCCCh followed by the new configuration data to the WDTCON register. Provided they
do not include access to the WDTCON register, any number of operations may be performed
between these two words, including memory and I/O reads and writes.
Writing AAAAh then 5555h to the WDTCON register resets the current count. This count
cannot be read. Provided they do not include access to the WDTCON register, any number of
operations may be performed between these two words, including memory and I/O reads and
writes. Use of these sequences is intended to prevent executing code from blocking a WDT
event. With the WDT, a maximum 1.67-second timeout period is possible in a 40-MHz system.
The WDT can be programmed to generate either an NMI or a system reset when it times out. If
programmed to generate an NMI, the NMIFLAG (Bit [12]) in the WDTCON register will be set
when it occurs. This flag should be tested by the NMI interrupt service routine (ISR) to establish
whether the WDT or an external source generated the interrupt. If set by writing the 3333h and
CCCCh sequence followed by the configuration data that includes clearing NMIFLAG, the ISR
should clear this flag. If the NMIFLAG is set while a second WDT timeout occurs, a WDT
system reset is generated in place of a second NMI interrupt.
The RSTFLAG (Bit [13]) in the WDTCON register is set if a WDT reset is generated, due to one
WDT occurrence while the WDT is programmed to generate resets, or because a WDT event
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