IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
2.2.36 rts0_n/rtr0_n/pio20—Ready-to-Send 0 (asynchronous output)/Ready-
to-Receive 0 (asynchronous input) .................................................................41
2.2.37 rxd0_n/pio23—Receive Data 0 (asynchronous input) ...................................41
2.2.38 rxd1_n/pio28—Receive Data 1 (asynchronous input) ...................................41
2.2.39 s2_n–s0_n—Bus Cycle Status (synchronous outputs with tristate) ...............41
2.2.40 s6/lock_n/clkdiv2_n/pio29—Bus Cycle Status Bit [6] (synchronous
output)/Bus Lock (synchronous output)/Clock Divide by 2 (input with
internal pullup)................................................................................................42
2.2.41 srdy/pio6—Synchronous Ready (synchronous level-sensitive input)............42
2.2.42 tmrin0/pio11—Timer Input 0 (synchronous edge-sensitive input) ................42
2.2.43 tmrin1/pio0—Timer Input 1 (synchronous edge-sensitive input) ..................43
2.2.44 tmrout0/pio10—Timer Output 0 (synchronous output) .................................43
2.2.45 tmrout1/pio1—Timer Output 1 (synchronous output) ...................................43
2.2.46 txd0/pio22—Transmit Data 0 (asynchronous output)....................................43
2.2.47 txd1/pio27—Transmit Data 1 (asynchronous output)....................................43
2.2.48 ucs_n/once1_n—Upper Memory Chip Select (synchronous
output)/ONCE Mode Request 1 (input with internal pullup) .........................43
2.2.49 uzi_n/pio26—Upper Zero Indicate (synchronous output)..............................44
2.2.50 vcc—Power Supply (input)..............................................................................44
2.2.51 whb_n (IA186ES only)—Write High Byte (synchronous output with
tristate)............................................................................................................44
2.2.52 wlb_n/wb_n—Write Low Byte (IA186ES only) (synchronous output
with tristate)/Write Byte (IA188ES only) (synchronous output with
tristate)............................................................................................................44
2.2.53 wr_n—Write Strobe (synchronous output) ....................................................44
2.2.54 x1—Crystal Input ...........................................................................................44
2.2.55 x2—Crystal Input ...........................................................................................44
2.3 Pins Used by Emulators ..............................................................................................45
Maximum Ratings, Thermal Characteristics, and DC Parameters .......................................45
Device Architecture..............................................................................................................47
4.1 Bus Interface and Control ...........................................................................................47
4.2 Clock and Power Management ...................................................................................49
4.3 System Clocks.............................................................................................................49
4.4 Power-Save Mode .......................................................................................................50
4.5 Initialization and Reset................................................................................................50
4.6 Reset Configuration Register ......................................................................................50
4.7 Chip Selects.................................................................................................................50
4.8 Chip-Select Timing .....................................................................................................50
4.9 Ready- and Wait-State Programming..........................................................................51
4.10 Chip-Select Overlap ....................................................................................................51
4.11 Upper-Memory Chip Select ........................................................................................52
4.12 Low-Memory Chip Select...........................................................................................52
3.
4.
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