IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
2.2.14 dt/r_n/pio4—Data Transmit or Receive (synchronous output with
tristate)............................................................................................................34
2.2.15 gnd—Ground ..................................................................................................35
2.2.16 hlda—Bus Hold Acknowledge (synchronous output)....................................35
2.2.17 int0—Maskable Interrupt Request 0 (asynchronous input)............................35
2.2.18 int1/select_n—Maskable Interrupt Request 1/Slave Select (both are
asynchronous inputs) ......................................................................................35
2.2.19 int2/inta0_n/pwd/pio31—Maskable Interrupt Request 2
(asynchronous input)/Interrupt Acknowledge 0 (synchronous
output)/Pulse Width Demodulator (Schmitt trigger input).............................36
2.2.20 int3/inta1_n/irq—Maskable Interrupt Request 3 (asynchronous
input)/Interrupt Acknowledge 1 (synchronous output)/Interrupt
Acknowledge (synchronous output)...............................................................36
2.2.21 int4/pio30—Maskable Interrupt Request 4 (asynchronous input)..................37
2.2.22 lcs_n/once0_n—Lower Memory Chip Select (synchronous output
with internal pullup)/ONCE Mode Request (input) .......................................37
2.2.23 mcs0_n/pio14—Midrange Memory Chip Select (synchronous output
with internal pullup) .......................................................................................37
2.2.24 mcs2_n–mcs1_n (pio24–pio 15)—Midrange Memory Chip Selects
(synchronous outputs with internal pullup) ....................................................37
2.2.25 mcs3_n/rfsh_n/pio25—Midrange Memory Chip Select (synchronous
outputs with internal pullup)/Automatic Refresh (synchronous output) ........38
2.2.26 nmi—Nonmaskable Interrupt (synchronous edge-sensitive input) ................38
2.2.27 pcs1_n–pcs0_n (pio17–pio16)—Peripheral Chip Selects 1–0
(synchronous outputs).....................................................................................38
2.2.28 pcs2_n/cts1_n/enrx1_n/pio18—Peripheral Chip Select 2
(synchronous output)/Clear-to-Send 1 (asynchronous input)/Enable-
Receiver-Request 1 (asynchronous input)......................................................39
2.2.29 pcs3_n/rts1_n/rtr1_n/pio18—Peripheral Chip Select 3 (synchronous
output)/Ready-to-Send 1 (asynchronous output)/Ready-to-Receive 1
(asynchronous input) ......................................................................................39
2.2.30 pcs5_n/A1/pio3—Peripheral Chip Select 5 (synchronous
output)/Latched Address Bit [1] (synchronous output)..................................40
2.2.31 pcs6_n/A2/pio2—Peripheral Chip Select 6 (synchronous
output)/Latched Address Bit [2] (synchronous output)..................................40
2.2.32 pio31–pio0—Programmable I/O Pins (asynchronous input/output
open-drain)......................................................................................................40
2.2.33 rd_n—Read strobe (synchronous output with tristate)...................................40
2.2.34 res_n—Reset (asynchronous level-sensitive input)........................................40
2.2.35 rfsh2_n/aden_n (IA188ES only)—Refresh 2 (synchronous output
with tristate)/Address Enable (input with internal pullup) .............................41
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