IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
Table 80. AC Characteristics Over Commercial Operating Ranges (40 MHz) (Continued)
No.
Name
Description
Min
Max
Read Cycle Timing Responses
24 tAZRL
25 tCLRL
26 tRLRH
27 tCLRH
28 tRHLH
29 tRHAV
30 tCLDOX
ad Address Float to rd_n Active
rd_n Active Delay
rd_n Pulse Width
0
0
–
10
–
10
–
tCLCL
0
tCLCH
tCLCL
0
rd_n Inactive Delay
rd_n Inactive to ale High
rd_n Inactive to ad Address Active
Data Hold Time
–
–
Write Cycle Timing Responses
31 tCVCTX
32 tWLWH
33 tWHLH
34 tWHDX
Control Inactive Delay
wr_n Pulse Width
wr_n Inactive to ale High
Data Hold after wr_n
0
2tCLCL
tCLCH
10
–
–
–
tCLCL
35 tWHDEX wr_n Inactive to den_n Inactive
tCLCH
–
41 tDSHLH
59 tRHDX
65 tAVWL
66 tAVRL
67 tCHCSV
68 tCHAV
87 tAVBL
ds_n Inactive to ale Inactive
tCLCH
–
–
–
–
9
8
rd_n High to Data Hold on ad Bus
a Address Valid to wr_n Low
a Address Valid to rd_n Low
clkouta High to lcs_n/usc_n Valid
clkouta High to a Address Valid
a Address Valid to whb_n/wlb_n Low
0
tCLCL + tCHCL
tCLCL + tCHCL
0
0
tCHCL -1.5
tCHCL
Refresh Timing Cycle Parameters
79 tCHRFD
82 tCLRF
85 tRFCY
86 tLCRF
clkin Timing
36 tCKIN
37 tCLCK
38 tCHCK
39 tCKHL
40 tCKLH
clkout Timing
42 tCLCL
43 tCLCH
44 tCHCL
clkouta High to rfsh_n Valid
clkouta High to rfsh_n Invalid
rfsh_n Cycle Time
0
0
12
12
–
6tCLCL
2tCLCL
lcs_n Inactive to rfsh_n Active Delay
–
x1 Period
25
7.5
7.5
–
66
–
–
5
5
x1 Low Time
x1 High Time
x1 Fall Time
x1 Rise time
–
clkouta Period
clkouta Low Time
clkouta High Time
25
TCLCL/2
TCLCL/2
–
–
–
45 tCH1CH2 clkouta Rise Time
–
–
–
–
–
3
3
0.5
25
35
46 tCL2CL1
61 tLOCK
69 tCICOA
70 tCICOB
clkouta Fall Time
Maximum PLL Lock Time
x1 to clkouta Skew
x1 to clkoutb Skew
®
IA211050831-19
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