XC835/836
Summary of Features
1
Summary of Features
The XC835/836 has the following features:
• High-performance XC800 Core
– compatible with standard 8051 processor
– two clocks per machine cycle architecture (for memory access without wait state)
– two data pointers
• On-chip memory
– 8 Kbytes of Boot ROM, Library ROM and User routines
– 256 bytes of RAM
– 256 bytes of XRAM
– 4/8 Kbytes of Flash (includes memory protection strategy)
• I/O port supply at 2.5 V - 5.5 V and core logic supply at 2.5 V (generated by
embedded voltage regulator)
8/4K Bytes
On-Chip Debug Support
XC800 Core
IIC
UART
SSC
Port 0
Port 1
Port 2
Port 3
8-bit Digital I/O
6-bit Digital I/O
Flash
Boot ROM
8K Bytes
Capture/Compare Unit
16-bit
XRAM
Compare Unit
16-bit
8-bit Digital/
Analog Input
256 Bytes
ADC
10-bit
RAM
3-bit Digital I/O
LED and Touch Sense Controller
256 Bytes
8-channel
Timer 0
16-bit
Timer 1
16-bit
Timer 2
16-bit
Real-Time Watchdog
Clock Timer
MDU
CORDIC
Figure 1
XC835/836 Functional Units
• Power-on reset generation
• Brownout detection for IO supply and core logic supply
• 48 MHz on-chip OSC for clock generation
– Loss-of-Clock detection
(more features on next page)
Data Sheet
1
V1.2, 2011-03
INFINEON [ Infineon ]
