XC835/836
General Device Information
2.3
Pin Configuration
The pin configuration of the XC835 in Figure 4.
P3.2/SPD_0/RXD_3/SDA_2/MTSR_5/
1
24
23
22
21
20
19
18
17
16
15
14
13
P3.0/XTAL4/SCL_2/SCK_1/EXINT2_1/COL6
MRST_5/EXINT0_6/T2EX_7/TXD_3
P0.7/SCL_3/LINE7/TSIN7/TXD_5/COUT63_0/
P3.1/XTAL3/RXD_4/RTCCLK/MTSR_4/
MRST_4/EXINT0_5/COLA_0/EXF2_1
2
COL3_1/COLA_3
P2.3/CCPOS0_2/CTRAP_2/T2_2/EXINT3/AN3
3
P0.3/CC60_1/SDA_1/CTRAP_0/LINE3/TSIN3
P2.2/CCPOS2_1/T12HR_3/T13HR_3/SCK_3/
T1_1/EXINT2_0/AN2
4
P0.2/T1_0/CC62_1/SCL_1/CCPOS2_0/LINE2/TSIN2
P0.1/T0_0/CC61_1/MTSR_3/MRST_2/T13HR_0/
CCPOS1_0/LINE1/TSIN1
P0.0/T2_0/T13HR_1/MTSR_2/MRST_3/T12HR_0/
CCPOS0_0/LINE0/TSIN0/COUT61_1
P2.1/CCPOS1_1/RXD_5/MTSR_6/T0_1/EXINT1_1/AN1
5
P2.0/CCPOS0_1/T12HR_2/T13HR_2/T2EX_3/
T2_1/EXINT0_3/AN0
6
XC835
P0.6/SPD_1/RXD_1/SDA_0/MTSR_1/MRST_0/EXINT0_1/
T2EX_0/LINE6/TSIN6/TXD_0/COL2_1/COLA_2
7
P1.5/CC62_0/COL5/COLA_1
P0.5/RXD_0/MTSR_0/MRST_1/EXINT0_0/LINE5/TSIN5/
COUT62_1/TXD_4/COL1_1/EXF2_3
8
P1.4/EXINT5/COL4/COUT62_0/COUT63_2
P0.4/T2EX_1/SCL_0/SCK_0/EXINT1_0/CTRAP_1/
LINE4/TSIN 4/EXF2_0/COL0_1/COL3_2/COLA_4
9
VDDC
VSSP
VDDP
10
11
12
P1.0/SPD_2/RXD_2/T2EX_2/EXINT0_2/COL0_0/
COUT60_0/TXD_1
P1.3/CC61_0/COL3_0/CC61_0/EXF2_2
P1.2/EXINT4/COL2_0/COUT61_0/COUT63_1
P1.1/CC60_0/COL1_0/TXD_2
Figure 4
XC835 Pin Configuration, PG-DSO-24 Package (top view)
Data Sheet
7
V1.2, 2011-03
INFINEON [ Infineon ]
