XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.10
A/D Converters
For analog signal measurement, up to two 10-bit A/D converters (ADC0, ADC1) with 16
(or 8) multiplexed input channels including a sample and hold circuit have been
integrated on-chip. They use the method of successive approximation. The sample time
(for loading the capacitors) and the conversion time are programmable and can thus be
adjusted to the external circuitry. The A/D converters can also operate in 8-bit conversion
mode, where the conversion time is further reduced.
Several independent conversion result registers, selectable interrupt requests, and
highly flexible conversion sequences provide a high degree of programmability to fulfill
the requirements of the respective application. Both modules can be synchronized to
allow parallel sampling of two input channels.
For applications that require more analog input channels, external analog multiplexers
can be controlled automatically.
For applications that require less analog input channels, the remaining channel inputs
can be used as digital input port pins.
The A/D converters of the XC228x support two types of request sources which can be
triggered by several internal and external events.
•
Parallel requests are activated at the same time and then executed in a predefined
sequence.
•
Queued requests are executed in a user-defined sequence.
In addition, the conversion of a specific channel can be inserted into a running sequence
without disturbing this sequence. All requests are arbitrated according to the priority level
that has been assigned to them.
Data reduction features, such as limit checking or result accumulation, reduce the
number of required CPU accesses and so allow the precise evaluation of analog inputs
(high conversion rate) even at low CPU speed.
The Peripheral Event Controller (PEC) may be used to control the A/D converters or to
automatically store conversion results into a table in memory for later evaluation, without
requiring the overhead of entering and exiting interrupt routines for each data transfer.
Therefore, each A/D converter contains 8 result registers which can be concatenated to
build a result FIFO. Wait-for-read mode can be enabled for each result register to
prevent loss of conversion data.
In order to decouple analog inputs from digital noise and to avoid input trigger noise
those pins used for analog input can be disconnected from the digital input stages under
software control. This can be selected for each pin separately via registers P5_DIDIS
and P15_DIDIS (Port x Digital Input Disable).
The Auto-Power-Down feature of the A/D converters minimizes the power consumption
when no conversion is in progress.
Data Sheet
59
V0.91, 2007-02
Draft Version
INFINEON [ Infineon ]
