TDA5235
Functional Description
2.8
Digital Control (SFR Registers)
SFR Address Paging
2.8.1
An SPI instruction allows a maximum address space of 8 bit. The address space for
supporting more than one configuration set is exceeding this 8 bit address room.
Therefore a page switch is introduced, which can be applied via register SFRPAGE (see
Figure 92).
logical address space
physical address space
0x000
0
d
Configuration A1) - Page 0
Configuration A 1) - Page 0
Reserved 2)
Reserved 2)
0x080
128d
Common Registers3)
Common Registers3)
Reserved 4)
Reserved 4)
0x0FF
0x100
255d
256d
Configuration B1) - Page 1
Configuration B 1) - Page 1
Reserved 2)
Reserved 2)
0x180
0x1FF
384d
511d
Common Registers3)
Reserved 4)
1)
Configuration dependent register block (2 protocol specific sets)
page switch via SFRPAGE register
Reserved – Forbidden area
2), 4)
3)
Configuration independent registers (common for all configurations )
map (“mirror“) to the same physical address space
Figure 92
2.8.2
SFR Address Paging
SFR Register List and Detailed SFR Description
The register list is attached in the Appendix at the end of the document.
Registers for Configuration B are equivalent and not shown in detail.
All registers with prefix “A_” are related to Configuration A. All these registers are also
available for Configuration B having the prefix “B_”.
Data Sheet
127
V1.0, 2010-02-19
INFINEON [ Infineon ]
