TC1767
Introduction
• Each SRN can be mapped to the CPU or PCP interrupt system
• Flexible interrupt-prioritizing scheme with 255 interrupt priority levels per SRN to
choose from
2.3.2
Direct Memory Access Controller
The TC1767 includes a fast and flexible DMA controller with independant DMA channels
( DMA Move engine).
Features
•
independent DMA channels
– Up to 16 selectable request inputs per DMA channel
– 2-level programmable priority of DMA channels within the DMA Sub-Block
– Software and hardware DMA request
– Hardware requests by selected on-chip peripherals and external inputs
• 3-level programmable priority of the DMA Sub-Block at the on chip bus interfaces
• Buffer capability for move actions on the buses (at least 1 move per bus is buffered)
• Individually programmable operation modes for each DMA channel
– Single Mode: stops and disables DMA channel after a predefined number of DMA
transfers
– Continuous Mode: DMA channel remains enabled after a predefined number of
DMA transfers; DMA transaction can be repeated
– Programmable address modification
– Two shadow register modes (with / w/o automatic re-set and direct write access).
• Full 32-bit addressing capability of each DMA channel
– 4 Gbyte address range
– Data block move supports > 32 Kbyte moves per DMA transaction
– Circular buffer addressing mode with flexible circular buffer sizes
• Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit
• Register set for each DMA channel
– Source and destination address register
– Channel control and status register
– Transfer count register
• Flexible interrupt generation (the service request node logic for the MLI channel is
also implemented in the DMA module)
• DMA module is working on SPB frequency, LMB interface on LMB frequency.
• Dependant on the target/destination address, Read/write requests from the Move
Engine are directed to the SPB, LMB, MLI or to the the Cerberus.
Data Sheet
18
V1.3, 2009-09
INFINEON [ Infineon ]
