C167CR
C167SR
External XRAM Access
If XPER-Share mode is enabled the on-chip XRAM of the C167CR can be accessed
(during hold states) by an external master like an asynchronous SRAM.
Table 19
XRAM Access Timing (Operating Conditions apply)1)
Symbol Limits
Parameter
Unit
min.
max.
–
Address setup time before RD/WR falling edge
Address hold time after RD/WR rising edge
Data turn on delay after RD falling edge
Data output valid delay after address latched
Data turn off delay after RD rising edge
Write data setup time before WR rising edge
Write data hold time after WR rising edge
WR pulse width
t40 SR 4
t41 SR 0
t42 CC 1
t43 CC –
t44 CC 1
t45 SR 10
t46 SR 2
t47 SR 20
t48 SR t40
ns
ns
ns
ns
ns
ns
ns
ns
ns
–
–
40
14
–
–
–
WR signal recovery time
–
1)
The minimum access cycle time is 60 ns.
t40
t41
Address
t47
t48
Command
(RD, WR)
t46
t45
Write Data
t43
t42
t44
Read Data
MCT04423
Figure 22
External Access to the XRAM
Data Sheet
68
V3.2, 2001-07
INFINEON [ Infineon ]
