C167CR
C167SR
Table 7
Name
C167CR Registers, Ordered by Name (cont’d)
Physical 8-Bit Description
Reset
Value
Address
b FFCAH
b FFCEH
b FFD2H
b FFD6H
FE00H
Addr.
E5H
E7H
E9H
EBH
00H
01H
02H
03H
DP4
Port 4 Direction Control Register
Port 6 Direction Control Register
Port 7 Direction Control Register
Port 8 Direction Control Register
CPU Data Page Pointer 0 Reg. (10 bits)
CPU Data Page Pointer 1 Reg. (10 bits)
CPU Data Page Pointer 2 Reg. (10 bits)
CPU Data Page Pointer 3 Reg. (10 bits)
External Interrupt Control Register
CPU Multiply Divide Control Register
CPU Multiply Divide Reg. – High Word
CPU Multiply Divide Reg. – Low Word
Port 2 Open Drain Control Register
Port 3 Open Drain Control Register
Port 6 Open Drain Control Register
Port 7 Open Drain Control Register
Port 8 Open Drain Control Register
Constant Value 1’s Register (read only)
Port 0 High Reg. (Upper half of PORT0)
Port 0 Low Reg. (Lower half of PORT0)
Port 1 High Reg. (Upper half of PORT1)
Port 1 Low Reg. (Lower half of PORT1)
Port 2 Register
00H
00H
DP6
DP7
00H
DP8
00H
DPP0
DPP1
DPP2
DPP3
EXICON
MDC
MDH
MDL
ODP2
ODP3
ODP6
ODP7
ODP8
ONES
P0H
0000H
0001H
0002H
0003H
0000H
0000H
0000H
0000H
0000H
0000H
00H
FE02H
FE04H
FE06H
b F1C0H E E0H
b FF0EH
FE0CH
87H
06H
07H
FE0EH
b F1C2H E E1H
b F1C6H E E3H
b F1CEH E E7H
b F1D2H E E9H
b F1D6H E EBH
00H
00H
FF1EH
b FF02H
b FF00H
b FF06H
b FF04H
b FFC0H
b FFC4H
b FFC8H
b FFA2H
8FH
81H
80H
83H
82H
E0H
E2H
E4H
D1H
D2H
E6H
E8H
EAH
FFFFH
00H
P0L
00H
P1H
00H
P1L
00H
P2
0000H
0000H
00H
P3
Port 3 Register
P4
Port 4 Register (8 bits)
P5
Port 5 Register (read only)
XXXXH
0000H
00H
P5DIDIS b FFA4H
Port 5 Digital Input Disable Register
Port 6 Register (8 bits)
P6
P7
P8
b FFCCH
b FFD0H
b FFD4H
Port 7 Register (8 bits)
00H
Port 8 Register (8 bits)
00H
Data Sheet
39
V3.2, 2001-07
INFINEON [ Infineon ]
