C167CR
READY
waitstate
6)
1)
MUX/Tristate
Running cycle
t32
t33
CLKOUT
ALE
t30
t34
t29
t31
7)
2)
Command
RD, WR
t35
t36
t35
t36
Sync
READY
3)
3)
4)
t58
t59
t58
t59
t60
Async
3)
3)
READY
t37
5)
see 6)
Figure 16
CLKOUT and READY
Notes
1)
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
The leading edge of the respective command depends on RW-delay.
2)
3)
READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
4)
5)
READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is guaranteed,
if READY is removed in response to the command (see Note 4)).
6)
7)
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
The next external bus cycle may start here.
Semiconductor Group
61
INFINEON [ Infineon ]
