C167CR
AC Characteristics
Demultiplexed Bus
VCC = 5 V ± 10 %;
VSS = 0 V
TA = 0 to + 70 ˚C
for SAB-C167CR-LM
TA = − 40 to + 85 ˚C for SAF-C167CR-LM
TA = − 40 to + 125 ˚C for SAK-C167CR-LM
CL (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
CL (for Port 6, CS) = 100 pF
ALE cycle time = 4 TCL + 2tA + tC + tF (100 ns at 20-MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 20 MHz
Variable CPU Clock
1/2TCL = 1 to 20 MHz
Unit
min.
CC 15 + tA
max.
min.
max.
ALE high time
t5
t6
–
–
–
TCL – 10 + tA
TCL – 15 + tA
–
–
–
ns
ns
ns
CC
CC
Address setup to ALE
10 + tA
15 + tA
t8
ALE falling edge to RD,
WR (with RW-delay)
TCL – 10
+ tA
t9
CC
ALE falling edge to RD,
WR (no RW-delay)
– 10 + tA
–
– 10
+ tA
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RD, WR low time
(with RW-delay)
t12 CC 40 + tC
t13 CC 65 + tC
–
2TCL – 10
+ tC
RD, WR low time
(no RW-delay)
–
3TCL – 10
+ tC
RD to valid data in
(with RW-delay)
t14 SR
t15 SR
t16 SR
t17 SR
t18 SR
–
–
–
–
0
–
–
30 + tC
55 + tC
–
–
–
–
0
–
–
2TCL – 20
+ tC
RD to valid data in
(no RW-delay)
3TCL – 20
+ tC
ALE low to valid data in
55
+ tA + tC
3TCL – 20
+ tA + tC
Address to valid data in
70
+ 2tA + tC
4TCL – 30
+ 2tA + tC
Data hold after RD
rising edge
–
–
Data float after RD rising t20 SR
35 + tF
2TCL – 15
+ 2tA + tF
1)
1)
edge (with RW-delay )
Data float after RD rising t21 SR
15 + tF
TCL – 10
+ 2tA + tF
1)
1)
edge (no RW-delay )
Data valid to WR
t22 CC 25 + tC
t24 CC 15 + tF
–
–
2TCL – 25
+ tC
–
Data hold after WR
TCL – 10 + tF
–
Semiconductor Group
54
INFINEON [ Infineon ]
