SAB 82525
SAB 82526
SAF 82525
SAF 82526
Receive HDLC Control Register (READ)
7
0
RHCR
RHCR
(29/69)
Value of the HDLC control field corresponds to the last received frame.
Note: RHCR is duplicated into RFIFO for every frame.
Contents of RHCR
Mode
Modulo 8 (MCS = 0)
Modulo 128 (MCS = 1)
Auto-mode,1-byte address
(U-frames) (Note 1)
Control field
Control field
(Note 2)
Auto-mode, 2-byte address Control field
(U-frames) (Note 1)
Control field
(Note 2)
Auto-mode, 1-byte address Control field
Control field in
(I-frames) (Note 1)
compressed form (Note 3)
Auto-mode, 2-byte address Control field
Control field in
(I-frames) (Note 1)
compressed form (Note 3)
2nd byte after flag
3rd byte after flag
3rd byte after flag
2nd byte after flag
Non-auto mode,
1-byte address
Non-auto mode,
2-byte address
Transparent
mode 1
Transparent
mode 0
Note 1: S-frames are handled automatically and are not transferred to the microprocessor.
Note 2: For U-frames (bit 0 of RHCR = 1) the control field is as in the modulo 8 case.
Note 3: For I-frames (bit 0 of RHCR = 0) the compressed control field has the same format
as in the modulo 8 case, but only the three LSB’s of the receive and transmit
counters are visible:
bit
7
6
5
4
3
2
1
0
N(R)
N(S)
P
0
Semiconductor Group
98