SAB 82525
SAB 82526
SAF 82525
SAF 82526
Receive Address Byte High Register 1 (WRITE)
7
0
RAH1
RAH1
CRI
0
(26/66)
In operating modes that provide high byte address recognition, the high byte of the received
address is compared with the individual programmable values in RAH1, or RAH2.
RAH1 … Value of the first individual high address byte
CRI … Command/Response Interpretation (auto-mode and non-auto mode only)
The setting of the CRI bit affects the meaning of the C/R bit in RSTA as follows:
C/R meaning
C/R value
Commands received
Responses received
0
1
1
0
CRI = 1
CRI = 0
Important: If the 1 byte address field is selected in auto-mode, RAH1 must be set to 00 .
H
Receive Address Byte High Register 2 (WRITE)
70
1
0
RAH2
RAH2
MCS
0
(27/67)
RAH2 … Value of second individual programmable high address byte.
MCS … Module Count Select; valid in auto-mode only.
The MCS bit adjusts the control field format according to the HDLC (ISDN/LAPD).
0 … basic operation (modulo 8)
1 … extended operation (modulo 128)
Note: When modulo 128 is selected, in auto-mode the "RHCR" register contains compressed
information of the extended control field (see RHCR, register description). RAH1, RAH2
registers are used in auto and non-auto operating modes when a 2-byte address field
has been selected (MODE.ADM = 1) and in the transparent mode 0.
RAH2 has to be initialized.
Semiconductor Group
94