PEB 2091
PEF 2091
Operational Description
4.4.2.1 LT Modes State Diagram
DR
SL0/SP
SL0
-
-
Test
Deactivated
DI
TN & DC
ARL
T2E
Any State
Pin-SSP or
Pin-RES or
Pin (PS1=1) or
µP-SSP or
µP-RES or
SSP or RES or
PFOFF or LTD
HI
DEAC
(AR or AR0 or ARX
or UAR) & /TN
T1S,
T2S
RES or
RES1
Pin PS1=1
T1S, T2S
TL
SL0
-
-
T2S
Alerting
DI
Reset for Loop
DI
T2E
T3S
T2S
T3E
SL0
-
RES1
Wait for TN
DI
EI3
T1E
T1S, T4S
TN or TL
(Loop)
Legend
IN
T9S,
T4S
SL0
SL0
-
-
T4S,
T1S
Awake
AR
LSEC or
T4E
SL1
Awake Error
AR
Signal to U
SB to U
T1S
T9E &
State Name
T9E &
/(LSEC or T4E)
T5S
CI-Code Indication (DU)
(LSEC or T4E)
-
T1S, T5S
EC-Training
AR
OUT
LSEC or T5E
T6S
SL2
a=0,d=1
EC-Converged
ARM
SEC or T6E or ARL
SL2
a=0,d=1
ARM
RES1
EQ-Training
EI3
SFD & (BBD1 or BBD0 or CRCOK)
& (/T1E or ARX)
T1E
SL3T
Line Active
UAI/FJ
a=0,d=1
SL3T
a=1,d=1
Pend. Transparent
UAI/FJ
DR or LOF
or LSUE
DR or LOF
or LSUE
act=1 & /AR0
T8S
T8E
UAR
AR0
Any State
Pin-DT, µP-DT or DT
AR0
a=0,d=1
S/T Deactivated
AR/FJ UAI/FJ
sai=0
sai=1
SL3T
SL3T
a=1,d=1
sai=0 & act = 0
DR or LOF
or LSUE
Transparent
DR or LOF
or LSUE
A//FJ
EI2/FJ
act=0
act=1
DR
LOF
T10S
LSUE
SL3T
a=0,d=1
SL3T
a=0,d=1
SL3T
a=0,d=0
Loss of Signal
LSL
Loss of Synchr.
RSY
Pend. Deactivation
DEAC
RES1
T10E
RES1
T7S
SL0
SL0
SL0
-
-
-
LSU
LSU
T7S
Receiver Reset
LSL
Tear Down Error
EI3/RSY
Tear Down
DEAC
T7E
TN
Figure 72
State Transition Diagram in LT Modes
Semiconductor Group
147
Data Sheet 01.99
INFINEON [ Infineon ]
