PEB 2091
PEF 2091
Operational Description
4.2.4
Setting Superframe Marker
In the NT and TE modes, with superframe marker selected (see "Setting Modes of
Operation (Stand-Alone and µP Mode)", page 51) the start of a new superframe is
indicated with a FSC high-phase lasting for one single DCL-period. A FSC high-phase
of two DCL-periods is transmitted for all other IOM®-2-frame starts.
In LT modes the superframe marker can be indicated by a short frame synchronization
signal (FSC) of the IOM®-2 interface. If the high phase of FSC lasts one DCL period or
less, the U-interface frame will be reset and the Inverted Synchronization Word (ISW)
will be inserted at the beginning of the next available basic frame. The remaining 95
FSC-clocks must be of at least two DCL-periods duration. If no superframe marker is to
be used, all FSC high-phases need to be of at least two DCL-periods duration.
The relationship between the IOM®-2-superframe marker of the slave, the U-interface,
and the IOM®-2 superframe marker of the master is fixed after activation of the
U-interface. I.e. data inserted on LT side in the first B1-channel after the IOM®-2-slave
superframe marker will always appear on the NT side with a fixed offset, e.g. in the 5th
B1-channel after the master superframe marker. After a new activation this relationship
(offset) may be different.
Superframe Marker Enable in µP Mode
Note 37: This feature is only available in the µP-LT Modes.
As mentioned above, in LT modes the superframe marker can be indicated by a short
frame synchronization signal (FSC) of the IOM®-2 interface. Consequently, spikes on
the FSC might be unintentionally recognized as superframe marker by the IEC-Q. In
most cases (> 85%) such a spike will introduce permanent high bit error rate. It is
therefore very important to make sure, that no spikes on pin FSC could occur. However,
cases were reported where spikes on pin FSC couldn’t be avoided.
Version 5.3 of the IEC-Q offers a way to overcome this problem. Setting bit SFEN of
register ADF2 (see "ADF2-Register", page 214) to "0" will disable the superframe marker
function. This prevents spikes on FSC to trigger superframes. Bit errors caused by the
additional FSC pulses will not last longer than 3 IOM®-2 frames.
Note 38: Setting ADF2:SFEN to "0" will introduce the same behavior as Version 5.2
(refer to the corresponding point in Delta Sheet of the PEB/F 2091 V5.2).
However, the value of ADF2:SFEN after reset will be "1", which means that
the superframe marker function is enabled by default and therefore
compatible to all IEC-Q versions up to 5.1.
Semiconductor Group
124
Data Sheet 01.99
INFINEON [ Infineon ]
