Low Level Controller
6.3.2.3 Register Bit Definitions
To facilitate reading and debugging of the code, the bits of many registers are defined as
follows:
The definitions
#define ISTA_RME
#define ISTA_RPF
#define ISTA_RSC
#define ISTA_XPR
#define ISTA_TIN
#define ISTA_CIC
#define ISTA_SIN
#define ISTA_EXI
(BYTE)0x80
(BYTE)0x40
(BYTE)0x20
(BYTE)0x10
(BYTE)0x08
(BYTE)0x04
(BYTE)0x02
(BYTE)0x01
specify the bits of the ISAC-S interrupt status register (ISTA).
6.4 Interrupts
Int_ICC is to be called in the case of ISAC-S interrupts. The following interrupts are handled
directly in Int_ICC:
’Transmit pool ready’ interrupt (ISTA:XPR)
’Timer’ interrupt (ISTA:TIN).
’Receive Status Change’ interrupt (ISTA:RSC).
’Extended’ interrupt (ISTA:EXI).
The ’Receive Pool Full’ (ISTA:RPF) and ’Receive Message End’ (ISTA:RME) interrupts are
handled by function RX_ICC. The ’CI or SQ channel change’ interrupt (ISTA:CISQ) is handled
by IntL1_SBC.
Please note that the following interrupts are not handled by the interrupt service routine
described here:
ISTA:SIN
(synchronous transfer interrupt)
EXIR:SOV (synchronous transfer overflow)
EXIR:MOS (monitor status) is handled by external functions which are not part of this
description.
EXIR:SAW (subscriber awake)
EXIR:WOV (watchdog timer overflow)
Semiconductor Group
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