Electrical Characteristics
DCL ( I )
t FSS
t FSH
FSC1/2 ( I )
FSD (O)
t FSW
t FDD
t IIH
t IIS
IDP0/1 ( I )
IDP0/1 (O)
SDS1/2 (O)
Bit 0
t IOD
Bit 0
t SDD
ITD00872
Figure 96
IOM® Timing (LT-S, LT-T, NT mode)
IOM® Timing
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
max.
IOM output data delay
IOM input data setup
t
t
IOD
IIS
20
20
140
100
ns
ns
IOM-1
IOM-2
4 + tWH
20
ns
ns
IOM-1
IOM-2
IOM input data hold
FSC1/2 strobe delay
Strobe signal delay
Bit clock delay
t
t
t
t
t
t
t
t
IIH
20
ns
ns
ns
ns
ns
ns
ns
ns
FSD
SDD
BCD
FSS
FSH
FSW
FDD
– 20
20
120
20
– 20
50
Frame sync setup
Frame sync hold
Frame sync width
FSD delay
30
40
20
140
Semiconductor Group
255
INFINEON [ Infineon ]
