BTS7040-1EPA
PROFET™ +2 12V
Power Stages
7.2.3
Output Voltage Limitation
To increase the current sense accuracy, VDS voltage is monitored. When the output current IL decreases while
the channel is diagnosed (DEN pin set to “high” - see Figure 18) bringing VDS equal or lower than VDS(SLC), the
output DMOS gate is partially discharged. This increases the output resistance so that VDS = VDS(SLC) even for
very small output currents. The VDS increase allows the current sensing circuitry to work more efficiently,
providing better kILIS accuracy for output current in the low range.
IN
t
DEN
tsIS(ON)
tsIS(OFF)
t
IL
t
VDS
VS
VDS(SLC)
t
PowerStage_GBR_diag.emf
Figure 18 Output Voltage Limitation activation during diagnosis
7.3
Advanced Switching Characteristics
7.3.1
Inverse Current behavior
When VOUT > VS, a current IINV flows into the power output transistor (see Figure 19). This condition is known
as “Inverse Current”.
If the channel is in OFF state, the current flows through the intrinsic body diode generating high power losses
therefore an increase of overall device temperature. If the channel is in ON state, RDS(INV) can be expected and
power dissipation in the output stage is comparable to normal operation in RDS(ON)
.
During Inverse Current condition, the channel remains in ON or OFF state as long as IINV < IL(INV)
.
With InverseON, it is possible to switch ON the channel during Inverse Current condition as long as IINV < IL(INV)
(see Figure 20).
Data Sheet
23
Rev. 1.10
2020-12-14
INFINEON [ Infineon ]
