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ILC1832M 参数 Datasheet PDF下载

ILC1832M图片预览
型号: ILC1832M
PDF下载: 下载PDF文件 查看货源
内容描述: μP监控电路 [レP SUPERVISORY CIRCUIT]
分类和应用: 光电二极管监控
文件页数/大小: 5 页 / 81 K
品牌: IMPALA [ Impala Linear Corporation ]
 浏览型号ILC1832M的Datasheet PDF文件第1页浏览型号ILC1832M的Datasheet PDF文件第2页浏览型号ILC1832M的Datasheet PDF文件第3页浏览型号ILC1832M的Datasheet PDF文件第5页  
µP Supervisory Circuit  
Preliminary  
Circuit Description  
Power Monitor  
Pushbutton Reset Input  
The RST and RST pins are asserted whenever VCC falls The PBRST input can be driven with a manual pushbutton  
switch or with external logic signals. The input is internally  
debounced and requires an active low signal to force the  
reset outputs into their active states. The PBRST input will  
recognize any pulse that is 20ms in duration or greater and  
will ignore all pulses that are less than 1ms in duration.  
below the reset threshold voltage set by the TOL pin. A 5%  
tolerance level (2.88V reset threshold voltage) can be  
selected by connecting the TOL pin to ground or a 10% tol-  
erance (2.55V reset threshold voltage) can be selected by  
connecting the TOL pin to VCC. The reset pins will remain  
asserted for a period of 250ms after VCC has resen above  
tPB  
the reset threshold voltage. The reset function ensures the  
microprocessor is properly reset and powers up into a  
known condition after a power failure. RST will remain valid  
with VCC as low as 1.4V.  
tPDLY  
PBRST  
RST  
tRST  
VCCTP  
VCCTP  
RST  
VCC  
tRPD  
RST  
RST  
Pushbutton Reset  
tRPU  
tTD  
Power-Up/Power-Down Sequence  
TD Pin  
GND  
Open  
VCC  
Min.  
Typ.  
Max.  
62.5 ms  
250 ms  
500 ms  
150 ms  
600 ms  
1200 ms  
250 ms  
1000 ms  
2000 ms  
Watchdog Timer  
The microprocessor can be monitored by connecting the ST  
pin (watchdog input) to a bus line or I/O line. If a high-to-  
low transition does not occur on the ST pin within the watch-  
dog timeout period set by the TD pin (see Table 1), the RST  
and RST pins will be asserted rsulting in a microprocessor  
reset. RST and RST will remain asserted for 250ms when  
this occurs. A minimum pulse of 75ns or any transition  
high-to-low on the ST pin will reset the watchdog timer. The  
watchdog timer will be reset if ST sees a valid transition  
within the watchdog timeout period.  
Alternate Source Reference Guide  
Industry P/N  
DS1832  
ILC Direct Replacement  
ILC1832N  
ILC1832M  
DS1832S  
tSD  
ST  
tTD  
Watchdog Input  
Impala Linear Corporation  
(408) 574-3939  
ILC1832 1.1  
www.impalalinear.com  
October 1999  
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