µP Supervisory Circuit
Preliminary
Pin Functions
Pin
Number
1
Pin
Name
PBRST
Description
Pushbutton reset input. This input is debounced and can be driven with external logic
signals or a mechanical pushbutton to actively force a reset. All pulses less than 1ms in
duration on the PBRST pin are ignored. Any pulse with a duration of 20ms or greater is
guaranteed to cause a reset. PBRST has an internal 40kΩ (typical) pull-up resistor to V
CC
.
Time delay input. This input selects the timebase used by the watchdog timer. When TD =
0V, the watchdog timeout period is set to a nominal value of 150ms, when TD = open, the
watchdog timeout period is set to a nominal value of 600ms and when TD = V
CC
, the
watchdog timeout period is 1.2 sec nominally.
Tolerance select input. Selects whether 5% or 10% of V
CC
is used as the reset threshold
voltage. When TOL = 0V, the 5% tolerance level is selected and when TOL = V
CC
, a 10%
tolerance level is selected.
Ground pin, 0V reference.
RST is asserted high if either V
CC
goes below the reset threshold, the watchdog times out or
PBRST is pulled low for a minimum of 20ms. RST remains asserted for one reset timeout
period after V
CC
exceeds the reset threshold or after the watchdog times out or after PBRST
goes high.
RST is asserted low if either V
CC
goes below the reset threshold, the watchdog times out or
PBRST is pulled low for a minimum of 20ms. RST remains asserted for one reset timeout
period after V
CC
exceeds the reset threshold or after the watchdog times out or after PBRST
goes high. Open-drain output.
Input to the watchdog timer. If ST does not see a transition from high to low within the
watchdog timeout period, RST and RST will be asserted.
Power supply input.
2
TD
3
TOL
4
5
GND
RST
6
RST
7
8
ST
V
CC
Block Diagram
V
CC
8
Trip Point
Select
+
-
Reset
Generator
6
RST
TOL
3
Ref
5
RST
PBRST
1
Manual Reset
Debounce
ST
7
Timeout
Select
Watchdog
Timer
4
TD
2
GND
Impala Linear Corporation
ILC1832 1.1
(408) 574-3939
www.impalalinear.com
October 1999
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