IMP1232LP/LPS
Application Information
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that is A HIGH-to-LOW ST signal transition must be regularly issued
“hung-up”. Through the time delay input, TD, three watchdog no later than the minimum time-out period defined by the state of
time-out periods are selectable: 150ms, 610ms and 1,200ms. If the the TD signal. This guarantees the watchdog timer does not
strobe input, ST, is not strobed LOW prior to timeout, reset signals time-out.
become active. On power-up or after the supply voltage returns to
Timeouts periods of approximately 150ms, 610ms or 1,200ms are
an in-tolerance condition, the reset signal remains active for
selected through the TD pin.
250ms minimum, allowing the power supply and system micro-
processor to stabilize.
Watchdog Time-Out Period (ms)
TD Voltage Level
ST Pulses as short as 20ns can be detected.
Min
62.5
250
500
Nominal
150
Max
250
Valid
Strobe
Valid
Strobe
Invalid
Strobe
GND
Floating
610
1000
2000
ST
V
1200
CC
1232_t03.eps
tST
tTD
The watchdog timer cannot be disabled. It must be strobed with a
high-to-low transition to avoid a watchdog timeout.
tRST
tTD
(Max)
(Min)
RESET
1232_09.eps
Note: ST is ignored whenever a reset is active.
Figure 5. Timing Diagram: Strobe Input
5V
IMP1232LP/LPS
8
7
6
5
1
2
3
4
MREQ
PBRST
TD
VCC
ST
10kΩ
µP
RESET
Address
Bus
Decoder
TOL
RESET
GND RESET
1232_07.eps
Figure 6. Application Circuit: Watchdog Timer
©
1999 IMP, Inc.
408-432-9100/ www.impweb.com
5
IMP [ IMP, INC ]
