IMP1 232LP/LPS
Absolute Maximum Ratings
Voltage on V
CC
. . . . . . . . . . . . . . . . . . . . . . . . –0.5V to 7V
Voltage on ST, TD . . . . . . . . . . . . . . . . . . . . . –0.5V to V
CC
+ 0.5V
Voltage on PBRST, RESET, RESET . . . . . . . . –0.5V to V
CC
+ 0.5V
Operating Temperature Range . . . . . . . . . . . –40°C to 85°C
(N/EMA version)
0°C to 70°C
Voltages measured with respect to ground.
These are stress ratings only and functional operation is not implied.
Soldering Temperature . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Storage Temperature . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Electrical Characteristics
Unless otherwise stated, 4.5V
≤
V
CC
≤
5.5V and over the operating temperature range of 0°C to +70°C (–40°C to +85°C for N/EMA
devices). All voltages are referenced to ground.
Parameter
Supply Voltage (V
CC
)
ST and PBRST Input High Level
ST and PBRST Input Low Level
V
CC
Trip Point (TOL = GND)
V
CC
Trip Point (TOL = V
CC
)
Watchdog Time-Out Period
Watchdog Time-Out Period
Watchdog Time-Out Period
Output Voltage
Output Current
Output Current
Input Leakage
RESET Low Level
Internal Pull-Up Resistor
Operating Current (CMOS)
Input Capacitance
Output Capacitance
PBRST Manual Reset
Minimum Low Time
Reset Active Time
ST Pulse Width
V
CC
Fail Detect to
RESET or RESET
V
CC
Slew Rate
PBRST Stable LOW to
RESET and RESET Active
V
CC
Detect to RESET or
RESET Inactive
V
CC
Slew Rate
Symbol
V
CC
V
IH
V
IL
V
CCTP
V
CCTP
t
TD
t
TD
t
TD
V
OH
I
OH
I
OL
I
IL
V
OL
Conditions
Min
4.5
2
– 0.3
4.50
4.25
Typ
Max
5.5
V
CC
+ 0.3V
0.8
Units
V
V
V
V
V
ms
ms
ms
V
mA
mA
4.62
4.37
150
1200
610
V
CC
- 0.1V
–10
4.74
4.49
250
2000
1000
TD = GND
TD = V
CC
TD floating
I = –500µA, Note 3
Output = 2.4V , Note 2
Output = 0.4V,
Note 1
Note 1
62.5
500
250
V
CC
- 0.5V
–8
10
–1.0
1.0
0.4
40
30
5
10
µA
V
kΩ
µA
pF
pF
ms
I
CC1
C
IN
C
OUT
t
PB
t
RST
t
ST
t
RPD
t
F
t
PDLY
t
RPU
t
R
t
RISE
= 5µs
4.25V to 4.75V
250
0
610
4.75V to 4.25V
300
Note 4
PBRST = V
IL
20
250
20
5
610
1000
8
ms
ns
µs
µs
20
1000
ms
ms
ns
Notes: 1. PBRST is internally pulled HIGH to V
CC
through a nominal 40kΩ resistor.
2. RESET is an open drain output.
3. RESET remains within 0.5V of V
CC
on power-down until V
CC
falls below 2V. RESET remains within 0.5V of ground on power-down
until V
CC
falls below 2.0V.
4. Must not exceed the minimum watchdog time-out period (t
TD
). The watchdog circuit cannot be disabled. To avoid a reset, ST must be
strobed.
©
1999 IMP, Inc.
408-432-9100/www.impweb.com
3
IMP [ IMP, INC ]
