Ei68C153
Bus Interrupter Module (VME)
Semiconductor, Inc.
3.
Respond internally
—
For this case,
Interrupt Acknowledge
IACKIN is asser-ted and a match is found.
The BIM completes the IACK cycle by sup
plying an interrupt vector from the proper
vector register followed by a DTACK signal
asserted because the interrupt acknowl
edge cycle is completed by this device. For
the BIM to respond in this mode of
operation, the EXTERNAL/INTERNAl con
trol register bit (X/IN) must be zero. For
each source of interrupt request, the asso
ciated control register determines the BIM
response to an IACK cycle, and the X/IN
bit sets this response either inter-nally
(X/IN =.0 ) or externally (X/IN = !).
The response of an interrupt Handler to a bus interrupt
request is an interrupt acknowledge cycle. The IACK
cycle is initiated in BIM by receiving IACK low R/W, A1,
A2, A3 are latched, and the interrupt level on line A1-A3
is compared with any interrupt requests pending in the
chip. Further activity can be one of four cases.
1.
No further action required — This occurs if
IACKIN is not asserted. Asserting IACKN
only starts the BIM activity. If the daisy
chain signal never reaches the BIM
(IACKIN is not asserted), another inter
rupter has responded to the IACK cycle.
The cycle will end, the IACK is negated,
and no additional action is required.
4.
Respond externally — For the final case,
IACKIN is also asserted, a match is found
and the associated control register has
X/IN bit set to one. The BIM does not
assert IACKOUT and does assert INTAE
low.INTAE signals that the requesting
device must com-plete the IACK cycle
(supplying a vector and DTACK) and that
the 2-bit code contained on outputs INTA
LO and INTAL1 shows which interrupt
source is being acknowledged
2.
Pass on the interrupt daisy chain — For
this case, IACKIN input is asserted by the
preceding daisy chain interrupter, and
IACKOUT output is in turn asserted. The
daisy chain signal is passed on when no
interrupts are pending on a matching level
or when any possible interrupts are dis
abled. The Interrupt Enable (IRE) bit of a
control register can disable any interrupt
requests, and in turn, any possible
matches
VERSAbus is a registered trademark of
MOTOROLA, INC.
VMEbus /VERSAbus INTERFACE BLOCK DIAGRAM
System Bus
IRQ1•
-IRQ7•
7
-5.0V
IRQ7
Data Bus
•
D0-D7
•
DO0-DO7
IRQ6
•
A1
A2
•
AO1
IRQ5
•
AO2
A3
•
AO3
R/W
IRQ4
•
WRITE•
•
DTACK
DTACK•
IRQ3
•
+5.0V
•
•
AO4-
A23
AMO-
AMX
IRQ2
•
•
EI68C153
BIM
Address
DEcode
IRQ1
INT0
Device A
Device B
Device C
Device D
CS
DSO•
AS•
INT1
INT2
Device
Interrupt
requests
IACK•
IACK
Control
Logic
SYSRESET•
}
INT3
IACKIN
IACKIN•
IACKOUT•
SYSCLK
INTAE
To Slave device
for external
IACKOUT
INTAL0
INTAL1
interrupt Ack-
knowledge
}
•
20
IMP [ IMP, INC ]
