Ei68C153
Bus Interrupter Module (VME)
Semiconductor, Inc.
FEATURES
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Programmable interrupt controller for
VMEbus and VERSAbus ™ systems
Receives and prioritizes 4 independent
local interrupt sources
7 programmable interrupt request levels for
each local interrupt source
Separate control and vector registers for
each local interrupt source
Interrupt enable and interrupt clear bits
Two response modes: Internal (vectored
mode) or external (interrupting device-sup
plies-the-vector mode)
Interrupt acknowledge daisy chain
Flag bits with auto-clear capability
Pin & function compatible with Motorola
MC68153
Single 5.0 volt power supply
Advanced CMOS low-power technology
DESCRIPTION
The Bus Interrupter Module (BIM) provides an interface
between interrupting devices and a system bus such as
the VMEbus or VERSAbus™. It generates a maximum
of 7 bus interrupts on the IRQ1-IRQ7 outputs and
responds to interrupt acknowledge cycles for up to 4
independent slaves. The BIM can also supply an inter-
rupt vector during an interrupt acknowledge cycle.
Moreover, it sits in the interrupt acknowledge daisy-
chain which allows for multiple interrupts on the level
acknowledged.
The BIM accepts device interrupt requests on inputs
INT0, INT1, INT2 and INT3. Each input is regulated by
Bit 4 (IRE) of the associated control register (CRO
controls INT0, CR! controls INT1,etc.). If IRE (Interrupt
Enable) is set and a device input is asserted, an
Interrupt Request open-collector output (IRQ1 - IRQ7)
is asserted. The asserted IRQX output is selected by
the value programmed in Bits 0, 1, and 2 of the control
register (L0, L1, and L3).
This 3-bit field determines the interrupt request level as
set by software.
Two or more interrupt sources can be programmed to
the same request level. The corresponding IRQX out-
put will remain asserted until multiple interrupt acknowl-
edge cycles respond to all requests.
If the interrupt request level is set to zero, the interrupt is
disabled because there is no corresponding IRQ output.
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Part Numbers May Be Marked With "IMP" or "Ei."
PIN CONFIGURATION
VCC
R/W
CS
DTACK
IACK
IACKIN
IACKOUT
IRQ1
GND
GND
VCC
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
CLK
INT0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A3
A2
A1
D7
D6
D5
D4
D3
D2
GND
VCC
D1
D0
INTAE
INTAL1
INTAL0
INT3
INT2
INT1
VCC/RST
E
I
6
8
C
1
5
3
40-PIN DIP
19
IMP [ IMP, INC ]
