Process C1004
Physical Characteristics
Starting Material
Starting Mat. Resistivity
Typ. Operating Voltage
Well Type
Metal Layers
Poly Layers
Contact Size
Via Size
Metal-1 Width/Space
Metal-2 Width/Space
Gate Poly Width/Space
P <100>
7-8.5
Ω-cm
5V
N-well
2
1
1.2x1.2µm
1.2x1.2µm
1.4 / 1.2µm
2.0 / 1.4µm
1.0 / 1.4µm
N+/P+ Width/Space
N+ To P+ Space
Contact To Poly Space
Contact Overlap Of Diffusion
Contact Overlap Of Poly
Metal-1 Overlap Of Contact
Metal-1 Overlap Of Via
Metal-2 Overlap Of Via
Minimum Pad Opening
Minimum Pad-to-Pad Spacing
Minimum Pad Pitch
2.0 / 1.2µm
7.0µm
0.8µm
0.7µm
0.7µm
0.7µm
0.7µm
0.7µm
65x65µm
5.0µm
80.0µm
Metal 2
Metal 1
SIO
2
LTO
LTO
n
+
p
+
Field Oxide
n
+
p
+
p
+
n
+
substrate contact
Poly gate
Poly gate
Source
Source
Drain
N-well contact
N-well
p
–
epi
p
+
substrate
Sidewall spacer
ID vs VD, W/L = 20/1.2
35.0
VGS = 5.0V
–15.0
ID vs VD, W/L = 20/1.2
VGS = –5.0V
Drain Current (mA) I
DS
Drain Current (mA) I
DS
28.0
VGS = 4.0V
–12.0
VGS = –4.0V
–9.0
21.0
VGS = 3.0V
14.0
VGS = 2.0V
7.0
VGS = 1.0V
0
0
1.0
2.0
3.0
4.0
5.0
Drain Voltage (V) V
DS
N-ch Transistor IV Characteristics of a 20/1.2 device
–6.0
p
–
Channel stop
Contact
Drain
LDD
p
p
VGS = –3.0V
–3.0
VGS = –2.0V
0
–1.0
–2.0
–3.0
–4.0
–5.0
0
Drain Voltage (V) V
DS
P-ch Transistor IV Characteristics of a 20/1.2 device
18
C1004-4-98
IMP [ IMP, INC ]
