IN16C1054
6. Functional Description
The IN16C1054 UART is pin-to-pin compatible with the TL16C554 and ST16C654
UARTs.
IN16C1054 offers 16C450 and 16C650 modes. When FIFO is enabled, it has a register
configuration compatible with 64-byte FIFO and 16C654, so it becomes compatible with
16C654. If you enable 256-byte FIFO, you use the unique supreme function that
IN16C1054 offers. It offers communication speed up to 5.3Mbps and more enhanced
functions that other UARTs with 128-byte FIFO do not.
IN16C1054 can select hardware/software flow control. Hardware flow control significantly
reduces software overhead and increases system efficiency by automatically controlling
serial data flow using the RTS# output and CTS# input signals. Software flow control
automatically controls data flow by using programmable Xon/Xoff characters.
6.1 FIFO Operation
IN16C1054’s FIFO has two modes, 64-byte FIFO mode and 256-byte FIFO mode. Setting
FCR[0] to ‘1’ enables FIFO, and if AFR[0] is set to ‘0’, it operates in 64-byte FIFO
mode(default). In this mode, Transmit Data FIFO, Receive Data and Receive Status FIFO
are 64 bytes. 64-byte FIFO mode allows you to select the Transmit Interrupt Trigger Level
from 8, 16, 32, or 56. You can verify this Interrupt Trigger Level by TTR and RTR. In this
mode TTR and RTR are Read Only.
And by FCR[5:4], XOFF Trigger Level can be selected to either 8, 16, 56, or 60, and XON
Trigger Level to either 0, 8, 16, or 56 by FCR[7:6]. You can verify XON and XOFF Trigger
Level by FUR and FLR. In 64-byte FIFO mode TTR and RTR are Read Only.
If you select 256-byte FIFO mode, you can experience more powerful features of
IN16C1054. Setting both FCR[0] and AFR[0] to ‘1’ will enable this mode. In this mode,
Transmit Data FIFO, Receive Data and Receive Status FIFO are 256 bytes. Interrupt
Trigger Level and XON, XOFF Trigger Level are controlled by TTR, RTR, FUR and FLR,
not by FCR[7:4]. That is, TTR, RTR, FUR and FLR can both read and write. You can
verify free space of Transmit FIFO and the number of characters received in Receive
FIFO by TCR, RCR and ISR[7:6].
While TX FIFO is full, the value sent to THR by CPU disappears. And while RX FIFO is
full, the data coming from external devices disappear as well, provided that flow control
function is not used.
For more information, refer to Register Description.
6.2 Hardware Flow Control
Hardware flow control is executed by Auto-RTS and Auto-CTS. Auto-RTS and Auto-CTS
can be enabled/disabled independently by programming EFR[7:6]. If Auto-RTS is
enabled, it reports that it cannot receive more data by asserting RTS# when the amount
of received data in RX FIFO exceeds the written value in FUR. Then after the data stored
in RX FIFO is read by CPU, it reports that it can receive new data by deasseting RTS#
when the amount of existing data in RX FIFO is less than the written value in FLR.
When Auto-CTS is enabled and CTS# is cleared to ‘0’, transmitting data to TX FIFO has
to be suspended because external device has reported that it cannot accept more data.
When data transmission has been suspended and CTS# is set to ‘1’, data in TX FIFO is
retransmitted because external device has reported that it can accept more data. These
operations prevent overrun during communication and if hardware flow control is disabled
and transmit data rate exceeds RX FIFO service latency, overrun error occurs.
Rev. 00
IKSEMICON [ IK SEMICON CO., LTD ]
