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IN16C1054 参数 Datasheet PDF下载

IN16C1054图片预览
型号: IN16C1054
PDF下载: 下载PDF文件 查看货源
内容描述: Quard UART,具有256字节FIFO [Quard Uart with 256-Byte FIFO]
分类和应用: 先进先出芯片
文件页数/大小: 53 页 / 654 K
品牌: IKSEMICON [ IK SEMICON CO., LTD ]
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IN16C1054  
Table 2: Pin Description…continued  
Name  
Pin  
Type  
Description  
TQFP80  
PLCC68  
14  
22  
48  
56  
11  
25  
45  
59  
12  
24  
46  
58  
10  
26  
44  
60  
17  
19  
51  
53  
7
RTS0#  
RTS1#  
RTS2#  
RTS3#  
CTS0#  
CTS1#  
CTS2#  
CTS3#  
DTR0#  
DTR1#  
DTR2#  
DTR3#  
DSR0#  
DSR1#  
DSR2#  
DSR3#  
DCD0#  
DCD1#  
DCD2#  
DCD3#  
RI0#  
26  
35  
66  
75  
23  
38  
63  
78  
24  
37  
64  
75  
22  
39  
62  
79  
29  
32  
69  
72  
17  
44  
57  
4
O
O
O
O
I
Request to Send (active low). These pins indicate that the  
UART is ready to send data to the modem, and affect  
transmit and receive operations only when Auto-RTS  
function is enabled.  
Clear to Send (active low). These pins indicate the modem  
is ready to accept transmitted data from the UART, and  
affect transmit and receive operations only when Auto-CTS  
function is enabled.  
I
I
I
O
O
O
O
I
Data Terminal Ready (active low). These pins indicate  
UART is ready to transmit or receive data.  
Data Set Ready (active low). These pins indicate modem is  
powered-on and is ready for data exchange with UART.  
I
I
I
I
Carrier Detect (active low). These pins indicate that a carrier  
has been detected by modem.  
I
I
I
I
Ring Indicator (active low). These pins indicate the modem  
has received a ringing signal from telephone line. A low to  
high transition on these input pins generates a modem  
status interrupt, if enabled.  
RI1#  
29  
41  
63  
I
RI2#  
I
RI3#  
I
Other Interfaces  
Name  
Pin  
Type  
Description  
TQFP80  
50  
PLCC68  
XTAL1  
XTAL2  
CLKSEL  
35  
36  
30  
I
Crystal or External Clock Input.  
51  
O
I
Crystal or Buffered Clock Output.  
45  
Clock Select. This pin selects the divide-by-1 or divide-by-4  
prescalable clock. During the reset, The high on CLKSEL  
selects the divide-by-1 prescaler. The low on CLK selects  
the divide-by-4 prescaler. The inverting value of CLKSEL is  
latched into MCR[7] at the trailing edge of RESET.  
Reset (active high). This pin will reset the internal registers  
and all the outputs.  
RESET  
53  
37  
I
VCC  
GND  
5, 25, 65  
13, 47, 64  
I
I
Power Supply Input. 3.3V (2.7V ~ 3.6V)  
16, 36, 56, 6, 23, 40,  
76 57  
Signal and Power Ground.  
NC  
10, 30, 47, 31  
52, 71  
-
No Internal Connection.  
Rev. 00  
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