IN16C1054
START
DATA(5-8)
PARITY STOP
RXDx
Sample
Clock
(FIFO AT OR ABOVE
TRIGGER LEVEL)
INTx(TRIGGER
LEVEL INTERRUPT
(FCR6, 7 = 0, 0)
(FIFO BELOW
TRIGGER LEVEL)
t
t
rint
sint
LSI INTERRUPT
t
IOR#
rint
(RD LSR)
IOR#
(RD RBR)
Figure 15: Receiver FIFO First Byte (Sets RBR) Timing
STOP
RXDx
Sample
Clock
(FIFO AT OR ABOVE
TRIGGER LEVEL)
TIMEOUT OR
TRIGGER LEVEL
INTERRUPT
(FIFO BELOW
TRIGGER LEVEL)
t
t
rint
sint
LSI INTERRUPT
TOP BYTE OF FIFO
t
t
rint
IOR#
sint
(RD LSR)
IOR#
(RD RBR)
PREVIOUS BYTE
READ FROM FIFO
Figure 16: Receiver FIFO After First Byte (After RBR Set) Timing
Rev. 00