MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
MPC940L DUT
ZO = 50Ω
ZO = 50Ω
Pulse
Generator
Z = 50Ω
RT = 50Ω
RT = 50Ω
VTT
VTT
Figure 1. LVCMOS_CLK MPC940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
MPC940L DUT
ZO = 50Ω
Differential Pulse
Generator
ZO = 50Ω
Z = 50Ω
RT = 50Ω
RT = 50Ω
VTT
VTT
Figure 2. PECL_CLK MPC940L AC Test Reference for VCC = 3.3 V and VCC = 2.5 V
VCC
PCLK_CLK
PCLK_CLK
V
CC ÷ 2
VCMR
LVCMOS_CLK
Q
VPP
GND
VCC
VCC
VCC÷2
V
CC ÷ 2
Q
GND
GND
tPD
tPD
Figure 4. LVCMOS Propagation Delay (tPD
)
Figure 3. Propagation Delay (tPD) Test Reference
Test Reference
VCC
VCC
V
CC ÷ 2
V
CC ÷ 2
GND
GND
VOH
tP
T0
V
CC ÷ 2
GND
DC = tP/T0 x 100%
tSK(O)
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage.
The pin-to-pin skew is defined as the worst case difference
in propagation delay between any two similar delay paths
within a single device.
Figure 6. Output-to-Output Skew TSK(O)
Figure 5. Output Duty Cycle (DC)
VCC = 3.3 V VCC = 2.5 V
VCC = 3.3 V VCC = 2.5 V
2.4
1.8 V
0.6 V
2.0
0.8
1.7 V
0.7 V
0.55
tF
tR
tF
tR
Figure 7. Output Transition Time Test Reference
Figure 8. Input Transition Time Test Reference
IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP
6
MPC940L REV 7 JUNE 5, 2007
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
