MPC940L
LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP
LOGIC DIAGRAM
PECL_CLK
0
1
PECL_CLK
Q0
LVCMOS_CLK
16
Q1–Q16
Q17
LVCMOS_CLK_SEL
(Internal Pulldown)
Pinout: 32-Lead LQFP (Top View)
24 23 22 21 20 19 18 17
GNDO
Q5
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCCO
Q12
FUNCTION TABLE
LVCMOS_CLK_SEL
Input
0
1
PECL_CLK
LVCMOS_CLK
Q4
Q13
Q3
Q14
MPC940L
VCCO
Q2
GNDO
Q15
POWER SUPPLY VOLTAGES
Supply Pin
Voltage Level
VCCI
VCCO
2.5 V or 3.3 V ± 5%
2.5 V or 3.3 V ± 5%
Q1
Q16
Q0
Q17
1
2
3
4
5
6
7
8
Table 1. Pin Configurations
Pin
PECL_CLK
PECL_CLK
LVCMOS_CLK
LVCMOS_CLK_SEL
Q0–Q17
I/O
Type
Function
Input
LVPECL
Reference Clock Input
Input
Input
LVCMOS
LVCMOS
LVCMOS
Supply
Alternative Reference Clock Input
Selects Clock Source
Output
Clock Outputs
VCCO
Output Positive Power Supply
Core Positive Power Supply
Output Negative Power Supply
Core Negative Power Supply
VCCI
Supply
GNDO
Supply
GNDI
Supply
IDT™ / ICS™ 1:18 CLOCK DISTRIBUTION CHIP
2
MPC940L REV 7 JUNE 5, 2007
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
