IDT71024
CMOS STATIC RAM 1MEG (128K x 8-BIT)
MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
t
RC
ADDRESS
tAA
OE
OE
t
(5)
tOLZ
CS1
CS2
(3)
t ACS
(5)
(5)
tOHZ
t CHZ
t CLZ
(5)
HIGH IMPEDANCE
DATA OUT
DATAOUT VALID
t PD
tPU
Vcc
Icc
Isb
SUPPLY
CURRENT
2964 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT VALID
PREVIOUS DATAOUT VALID
DATAOUT
2964 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS1 is LOW, CS2 is HIGH.
3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
