Description
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
The IDT7005 is a high-speed 8K x 8 Dual-Port Static RAM. The
IDT7005 is designed to be used as a stand-alone 64K-bit Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more
word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach
in 16-bit or wider memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT’s CMOS high-performance technology, these
devices typically operate on only 750mW of power. Low-power (L)
versions offer battery backup data retention capability with typical power
consumption of 500µW from a 2V battery.
The IDT7005 is packaged in a ceramic 68-pin PGA, 68-pin quad
flatpack, 68-pin PLCC and a 64-pin thin quad flatpack, (TQFP). Military
grade product is manufactured in compliance with the latest revision of MIL-
PRF-38535 QML making it ideally suited to military temperature applica-
tions demanding the highest level of performance and reliability.
11/16/01
INDEX
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O
1L
I/O
0L
N/C
OE
L
R/W
L
SEM
L
CE
L
N/C
N/C
V
CC
A
12L
A
11L
A
10L
A
9L
A
8L
A
7L
A
6L
9
8
7
6 5
4
3
2
1 68 67 66 65 64 63 62 61
60
59
58
57
56
Pin Configurations
(1,2,3)
IDT7005J or F
J68-1
(4)
F68-1
(4)
68 Pin PLCC / FLATPACK
Top View
(5)
55
54
53
52
51
50
49
48
47
46
45
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
2738 drw 02
,
I/O
7R
N/C
OE
R
R/W
R
SEM
R
CE
R
N/C
N/C
GND
A
12R
A
11R
A
10R
A
9R
A
8R
A
7R
A
6R
A
5R
R/W
L
SEM
L
I/O
1L
I/O
0L
OE
L
A
12L
A
11L
N/C
V
CC
CE
L
A
9L
A
8L
A
7L
INDEX
61
60
57
56
64
63
62
59
55
54
53
52
58
51
50
49
A
6L
A
5L
11/16/01
A
10L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
GND
I/O
0R
I/O
1R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
48
47
46
45
44
43
42
41
40
39
38
37
36
35
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
.
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
7005PF
PN-64
(4)
64-Pin TQFP
Top View
(5)
I/O
6R
I/O
7R
OE
R
R/W
R
SEM
R
A
9R
A
8R
A
7R
A
6R
A
12R
A
11R
GND
A
10R
CE
R
N/C
A
5R
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .12 in.
F68-1 package body is approximately .97 in x .97 in x .08 in.
PN64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
23
24
25
26
27
28
29
30
31
22
16
20
21
17
18
19
32
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
34
33
2738 drw 03
6.42
2
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
