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ICS501MT 参数 Datasheet PDF下载

ICS501MT图片预览
型号: ICS501MT
PDF下载: 下载PDF文件 查看货源
内容描述: [Clock Generator, 160MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8]
分类和应用: 时钟光电二极管外围集成电路晶体
文件页数/大小: 9 页 / 92 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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ICS501  
LOCO™ PLL CLOCK MULTIPLIER  
CLOCK MULTIPLIER  
Pin Assignment  
Clock Output Table  
S1 S0  
CLK  
4X input  
Minimum Input  
0
0
0
M
1
per page 5  
20 MHz  
X1/ICLK  
VDD  
8
7
6
5
1
2
3
4
X2  
5.3125X input  
5X input  
OE  
S0  
0
per page 5  
4 MHz  
M
M
M
1
0
6.25X input  
2X input  
GND  
S1  
M
1
per page 5  
8 MHz  
CLK  
3.125X input  
6X input  
0
per page 5  
per page 5  
per page 5  
8 Pin (150 mil) SOIC  
1
M
1
3X input  
1
8X input  
0 = connect directly to ground  
1 = connect directly to VDD  
M = leave unconnected (floating)  
Common Output Frequency Examples (MHz)  
Output  
Input  
20  
24  
12  
30  
10  
32  
16  
33.33  
16.66  
M, M  
37.5  
12  
40  
10  
48  
12  
50  
60  
62.5  
20  
10  
16.66  
1, M  
10  
Selection (S1, S0) M, M  
M, M  
1, M  
M, M  
M, 1  
0, 0  
0, 0  
1, 0  
M, 1  
Output  
64  
16  
66.66  
16.66  
0, 0  
72  
12  
75  
12  
80  
10  
83.33  
16.66  
0, 1  
90  
15  
100  
20  
106.25  
20  
120  
15  
125  
20  
Input  
Selection (S1, S0)  
0, 0  
1, 0  
M, 0  
1, 1  
1, 0  
0, 1  
0, M  
1, 1  
M, 0  
Pin Descriptions  
Pin Pin  
Number Name  
Pin  
Type  
Pin Description  
1
2
3
4
5
6
7
8
XI/ICLK  
VDD  
GND  
S1  
Input  
Power  
Power  
Crystal connection or clock input.  
Connect to +3.3 V or +5 V.  
Connect to ground.  
Tri-level Iinput  
Output  
Select 1 for output clock. Connect to GND or VDD or float.  
Clock output per table above.  
CLK  
S0  
Tri-level Input  
Input  
Select 0 for output clock. Connect to GND or VDD or float.  
OE  
Output enable. Tri-states CLK output when low. Internal pull-up.  
Crystal connection. Leave unconnected for clock input.  
X2  
Output  
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER  
2
ICS501  
REV Q 092209  
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