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9UMS9633BKILFT 参数 Datasheet PDF下载

9UMS9633BKILFT图片预览
型号: 9UMS9633BKILFT
PDF下载: 下载PDF文件 查看货源
内容描述: 超移动PC时钟为工业级温度范围 [ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE]
分类和应用: PC时钟
文件页数/大小: 22 页 / 211 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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ICS9UMS9633BI  
Advance Information  
ULTRA MOBILE PC CLOCK FOR INDUSTRIAL TEMPERATURE RANGE  
Byte  
Bit(s)  
0
PLL & Divider Enable Register  
Name  
Pin #  
Description  
Type  
0
1
Default  
This bit controls whether the PLL driving the CPU  
and SRC clocks is enabled or not.  
This bit controls whether the PLL driving the DOT  
and clock is enabled or not.  
This bit controls whether the PLL driving the LCD  
clock is enabled or not.  
7
6
-
-
PLL1 Enable  
PLL2 Enable  
PLL3 Enable  
RW  
0 = Disabled  
1 = Enabled  
1
RW  
RW  
0 = Disabled  
0 = Disabled  
1 = Enabled  
1 = Enabled  
1
5
4
-
-
1
0
Reserved  
This bit controls whether the CPU output divider is  
enabled or not.  
3
2
1
0
-
-
-
-
CPU Divider Enable  
RW  
RW  
RW  
RW  
0 = Disabled  
0 = Disabled  
0 = Disabled  
0 = Disabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1 = Enabled  
1
1
1
1
This bit should be automatically set to ‘0’ if  
bit 7 is set to ‘0’.  
NOTE:  
This bit controls whether the SRC output divider is  
enabled or not.  
NOTE: This bit should be automatically set to ‘0’ if  
bit 7 is set to ‘0’.  
This bit controls whether the LCD output divider is  
enabled or not.  
SRC Output Divider  
Enable  
LCD Output Divider  
Enable  
This bit should be automatically set to ‘0’ if  
bit 5 is set to ‘0’.  
NOTE:  
This bit controls whether the DOT output divider is  
enabled or not.  
DOT Output Divider  
Enable  
This bit should be automatically set to ‘0’ if  
bit 6 is set to ‘0’.  
NOTE:  
Byte  
Bit(s)  
1
PLL SS Enable/Control Register  
Name  
Pin #  
Description  
Type  
0
1
Default  
This bit controls whether PLL1 has spread enabled  
or not. Spread spectrum for PLL1 is set at -0.5%  
down-spread. Note that PLL1 drives the CPU and  
SRC clocks.  
7
6
PLL1 SS Enable  
RW  
0 = Disabled  
1 = Enabled  
1
This bit controls whether PLL3 has spread enabled  
or not. Note that PLL3 drives the SSC clock, and  
that the spread spectrum amount is set in bits 3-5.  
PLL3 SS Enable  
PLL3 FS Select  
RW  
RW  
0 = Disabled  
1 = Enabled  
1
5
4
3
2
1
0
These 3 bits select the frequency of PLL3 and the  
0
0
0
0
0
0
See Table 2: LCD Spread  
Select Table  
SSC clock when Byte 1 Bit 6 (PLL3 Spread  
Spectrum Enable) is set.  
Reserved  
Reserved  
Reserved  
IDTTM/ICSTM Ultra Mobile PC Clock for Industrial Temperature Range  
1451—01/20/09  
13  
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