ICS527-04
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB
PECL ZDB AND MULTIPLIER/DIVIDER
Pin Assignment
R5
R6
IR A N G E
S0
S1
VDD
FBPECL
FBPECL
GND
P E C L IN
P E C L IN
F0
F1
F2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R4
R3
R2
R1
R0
VDD
PECLO
PECLO
GND
RES
F6
F5
F4
F3
Output Frequency and Output
Divider Table
S1
Pin 5
0
0
1
1
S0
Pin 4
0
1
0
1
Output Frequency (MHz)
PECLO Output Pair
10 - 80
5 - 40
2.5 - 20
20 -160
IRANGE Setting Table
IRANGE
0
1
Criteria
if (FBPECL < 80 MHz) and (PECLIN < 80 MHz)
if (FBPECL > 80 MHz) or (PECLIN > 80 MHz)
28-pin (150 mil) SSOP
Pin Descriptions
Pin
Number
1-2
24 - 28
3
4-5
6, 23
7
8
9, 20
10
11
12 - 18
19
21
22
Pin
Name
R5, R6,
R0-R4
IRANGE
S0, S1
VDD
FBPECL
FBPECL
GND
PECLIN
PECLIN
F0-F6
RES
PECLO
PECLO
Pin
Type
Input
Input
Input
Power
Input
Input
Power
Input
Input
Input
BIAS
Output
Output
Pin Description
Reference divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up.
Set for proper frequency range of input clocks. See table above.
Select pins for output frequency range. See table above. Internal pull-up.
Connect to +3.3 V.
PECL feedback input to PLL.
PECL feedback input to PLL.
Connect to ground
PECL input clock.
Complementary PECL input clock.
Feedback divider word input pins determined by user. Forms a binary number
from 0 to 127. Internal pull-up
Resistor connection to VDD for setting level of PECL outputs.
Complementary PECL output.
PECL output. Rising edge aligns with PECLIN when connected directly to
FBPECL.
IDT™ / ICS™
CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB
2
ICS527-04
REV F 051310
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
